From 2b7504c27947a139473986fa65d977701addb88d Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 7 Apr 2008 10:48:44 +0000 Subject: - only if "reset halt" or "reset init" are issued will the reset vector be set up - If communication fails during assert between assert/deassert and during assert, warnings are printed. The warning suggests using srst_only if the clock locks up as that would allow the reset vector to be set up before asserting reset. git-svn-id: svn://svn.berlios.de/openocd/trunk@544 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm7_9_common.c | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) (limited to 'src/target/arm7_9_common.c') diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 4e14497d..d77f2000 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -736,7 +736,7 @@ int arm7_9_poll(target_t *target) /* Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock - while the core is held in reset. It isn't possible to program the halt + while the core is held in reset(SRST). It isn't possible to program the halt condition once reset was asserted, hence a hook that allows the target to set up its reset-halt condition prior to asserting reset. */ @@ -753,32 +753,34 @@ int arm7_9_assert_reset(target_t *target) return ERROR_FAIL; } - /* - * Some targets do not support communication while TRST is asserted. We need to - * set up the reset vector catch here. - * - * If TRST is in use, then these settings will be reset anyway, so setting them - * here is harmless. - */ - if (arm7_9->has_vector_catch) - { - /* program vector catch register to catch reset vector */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); - } - else + if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT)) { - /* program watchpoint unit to match on reset vector address */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7); + /* + * Some targets do not support communication while SRST is asserted. We need to + * set up the reset vector catch here. + * + * If TRST is asserted, then these settings will be reset anyway, so setting them + * here is harmless. + */ + if (arm7_9->has_vector_catch) + { + /* program vector catch register to catch reset vector */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); + } + else + { + /* program watchpoint unit to match on reset vector address */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7); + } } /* we can't know what state the target is in as we might e.g. * be resetting after a power dropout, so we need to issue a tms/srst */ - /* assert SRST and TRST */ /* system would get ouf sync if we didn't reset test-logic, too */ jtag_add_reset(1, 1); -- cgit v1.2.3