From 028f59ede54917d59f8183e6feac43cb0a6f3546 Mon Sep 17 00:00:00 2001 From: drath Date: Mon, 4 Sep 2006 10:31:28 +0000 Subject: - added debug output for D/I FSR and FAR (arm920t) - fixed bug that caused CPSR to be corrupted in Thumb mode git-svn-id: svn://svn.berlios.de/openocd/trunk@93 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/armv4_5.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/target/armv4_5.h') diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index ee37723e..0472155b 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -229,6 +229,17 @@ extern int armv4_5_invalidate_core_regs(target_t *target); */ #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16)) +/* Load multiple (Thumb state) + * Rn: base register + * List: for each bit in list: store register + */ +#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) + +/* Load register with PC relative addressing + * Rd: register to load + */ +#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) + /* Move hi register (Thumb mode) * Rd: destination register * Rm: source register @@ -237,7 +248,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); /* No operation (Thumb mode) */ -#define ARMV4_5_T_NOP (0x1c3f | (0x1c3f << 16)) +#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) /* Move immediate to register (Thumb state) * Rd: destination register -- cgit v1.2.3