From 3acb107b9ae4e3d38d3fcfd29b455ebcfb444696 Mon Sep 17 00:00:00 2001 From: drath Date: Thu, 31 Aug 2006 12:41:49 +0000 Subject: - endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts - added access to ARM920T vector catch register (via generic register mechanism) - don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache - read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands) - memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes) - made in_handler independent from in field (makes the handler more flexible) - added timeout to ft2232 when using D2XX library - fixed STR7x protection bit handling on second bank (thanks to Bernard) - added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen) - fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen) git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/armv4_5.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/target/armv4_5.h') diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index a28bfa12..ee37723e 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -193,6 +193,27 @@ extern int armv4_5_invalidate_core_regs(target_t *target); */ #define ARMV4_5_BX(Rm) (0xe12fff10 | Rm) +/* Move to ARM register from coprocessor + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) + +/* Move to coprocessor from ARM register + * CP: Coprocessor number + * op1: Coprocessor opcode + * Rd: destination register + * CRn: first coprocessor operand + * CRm: second coprocessor operand + * op2: Second coprocessor opcode + */ +#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) + + /* Thumb mode instructions */ -- cgit v1.2.3