From dfbb9f3e89ae6a3769d0df2167208c7c07e22e3c Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 21 Jul 2008 15:59:41 +0000 Subject: - jtag_khz/speed are now single parameter only. These are used from pre/post_reset event scripts. Adding the second parameter was a mistake seen in retrospect. this gives precise control in post_reset for *when* the post reset speed is set. The pre_reset event was added *after* the second parameter to jtag_khz/speed - the target implementations no longer gets involved in the reset mode scheme. Either they reset a target into a halted mode or not. target_process_reset() detects if the reset halt failed or not. - tcl target event names are now target_N_name. Mainly internal at this early stage, but best to get the naming right now. - added hardcoded reset modes from gdb_server.c. I don't know precisely what these defaults should be or if it should be made configurable. Perhaps some hardcoded defaults will do for now and it can be made configurable later. - bugfix in cortex_m3.c for reset_run_and_xxx? - issue syntax error upon obsolete argument in target command instead of printing message that will surely drown in the log git-svn-id: svn://svn.berlios.de/openocd/trunk@849 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/event/sam7s256_reset.script | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'src/target/event/sam7s256_reset.script') diff --git a/src/target/event/sam7s256_reset.script b/src/target/event/sam7s256_reset.script index 456341d6..1d389287 100644 --- a/src/target/event/sam7s256_reset.script +++ b/src/target/event/sam7s256_reset.script @@ -5,13 +5,19 @@ # # http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html # -mww 0xfffffd44 0x00008000 # disable watchdog -mww 0xfffffd08 0xa5000001 # enable user reset -mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +# disable watchdog +mww 0xfffffd44 0x00008000 +# enable user reset +mww 0xfffffd08 0xa5000001 +# CKGR_MOR : enable the main oscillator +mww 0xfffffc20 0x00000601 sleep 10 -mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz +# CKGR_PLLR: 96.1097 MHz +mww 0xfffffc2c 0x00481c0e sleep 10 -mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +mww 0xfffffc30 0x00000007 sleep 10 -mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +# MC_FMR: flash mode (FWS=1,FMCN=60) +mww 0xffffff60 0x003c0100 sleep 100 -- cgit v1.2.3