From d3f0549f08d8aac36143bca9e7f7e1308383b7c2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 3 Apr 2008 14:00:17 +0000 Subject: - Work on fixing erase check. Many implementations are plain broken. Wrote a default flash erase check fn which uses CFI's target algorithm w/fallback to memory reads. - "flash info" no longer prints erase status as it is stale. - "flash erase_check" now prints erase status. erase check can take a *long* time. Work in progress - arm7/9 with seperate srst & trst now supports reset init/halt after a power outage. arm7/9 no longer makes any assumptions about state of target when reset is asserted. - fixes for srst & trst capable arm7/9 with reset init/halt - prepare_reset_halt retired. This code needs to be inside assert_reset anyway - haven't been able to get stm32 write algorithm to work. Fallback flash write does work. Haven't found a version of openocd trunk where this works. - added target_free_all_working_areas_restore() which can let be of restoring backups. This is needed when asserting reset as the target must be assumed to be an unknown state. Added some comments to working areas API - str9 reset script fixes - some guidelines - fixed dangling callbacks upon reset timeout git-svn-id: svn://svn.berlios.de/openocd/trunk@536 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/event/str912_reset.script | 1 + 1 file changed, 1 insertion(+) (limited to 'src/target/event') diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script index 8178c82c..bbec5976 100644 --- a/src/target/event/str912_reset.script +++ b/src/target/event/str912_reset.script @@ -18,4 +18,5 @@ mww 0x54000018, 0x18 #Enable CS on both banks mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register +str9x flash_config 0 4 2 0 0x80000 flash protect 0 0 7 off -- cgit v1.2.3