From 30268bc40fb5f238b056a10b465cb9c13f466672 Mon Sep 17 00:00:00 2001
From: kc8apf <kc8apf@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 20 May 2009 05:07:34 +0000
Subject: Author: Spencer Oliver <spen@spen-soft.co.uk> - Bring the mips
 step/resume interrupt handling inline with the rest of openocd.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1850 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/mips32.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

(limited to 'src/target/mips32.c')

diff --git a/src/target/mips32.c b/src/target/mips32.c
index c109ed20..084e6276 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -420,3 +420,41 @@ int mips32_configure_break_unit(struct target_s *target)
 	
 	return ERROR_OK;
 }
+
+int mips32_enable_interrupts(struct target_s *target, int enable)
+{
+	int retval;
+	int update = 0;
+	u32 dcr;
+	
+	/* read debug control register */
+	if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+		return retval;
+	
+	if (enable)
+	{
+		if (!(dcr & (1<<4)))
+		{
+			/* enable interrupts */
+			dcr |= (1<<4);
+			update = 1;
+		}
+	}
+	else
+	{
+		if (dcr & (1<<4))
+		{
+			/* disable interrupts */
+			dcr &= ~(1<<4);
+			update = 1;
+		}
+	}
+	
+	if (update)
+	{
+		if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
+			return retval;
+	}
+	
+	return ERROR_OK;
+}
-- 
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