From 0bba832713cca8e5931d5d21f37f526d0a3979cf Mon Sep 17 00:00:00 2001 From: mifi Date: Sat, 18 Apr 2009 10:08:13 +0000 Subject: The following patches was applied: - openocd-flash-static-keyword-v3.patch - openocd-lpc2000-fix-erase-obo.patch - openocd-jlink-fix-sign-ptr-warn.patch - openocd-wextra-etm.patch - openocd-wextra-jtag.patch - openocd-add-new-tap-symbols-v6.patch Many thanks to Zach Welch git-svn-id: svn://svn.berlios.de/openocd/trunk@1462 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm11.c | 14 +++++++------- src/target/arm11_dbgtap.c | 48 +++++++++++++++++++++++------------------------ src/target/arm720t.c | 4 ++-- src/target/arm7tdmi.c | 12 ++++++------ src/target/arm920t.c | 8 ++++---- src/target/arm926ejs.c | 8 ++++---- src/target/arm966e.c | 6 +++--- src/target/arm9tdmi.c | 12 ++++++------ src/target/arm_jtag.c | 4 ++-- src/target/cortex_swjdp.c | 4 ++-- src/target/embeddedice.c | 14 +++++++------- src/target/embeddedice.h | 2 +- src/target/etb.c | 14 +++++++------- src/target/etm.c | 8 ++++---- src/target/feroceon.c | 4 ++-- src/target/mips_ejtag.c | 8 ++++---- src/target/xscale.c | 16 ++++++++-------- 17 files changed, 93 insertions(+), 93 deletions(-) (limited to 'src/target') diff --git a/src/target/arm11.c b/src/target/arm11.c index 39a6817d..7ccc7b82 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -383,9 +383,9 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) if (R(DSCR) & ARM11_DSCR_WDTR_FULL) { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID); - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); scan_field_t chain5_fields[3]; @@ -614,9 +614,9 @@ void arm11_leave_debug_state(arm11_common_t * arm11) if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID); scan_field_t chain5_fields[3]; @@ -1565,7 +1565,7 @@ int arm11_examine(struct target_s *target) /* check IDCODE */ - arm11_add_IR(arm11, ARM11_IDCODE, -1); + arm11_add_IR(arm11, ARM11_IDCODE, TAP_INVALID); scan_field_t idcode_field; @@ -1575,9 +1575,9 @@ int arm11_examine(struct target_s *target) /* check DIDR */ - arm11_add_debug_SCAN_N(arm11, 0x00, -1); + arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID); - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); scan_field_t chain0_fields[2]; diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index cfa8de64..9350a951 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -95,7 +95,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo * * \param arm11 Target state variable. * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions. - * \param state Pass the final TAP state or -1 for the default value (Pause-IR). + * \param state Pass the final TAP state or TAP_INVALID for the default value (Pause-IR). * * \remarks This adds to the JTAG command queue but does \em not execute it. */ @@ -120,7 +120,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) arm11_setup_field(arm11, 5, &instr, NULL, &field); - arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state); + arm11_add_ir_scan_vc(1, &field, state == TAP_INVALID ? TAP_IRPAUSE : state); } /** Verify shifted out data from Scan Chain Register (SCREG) @@ -152,7 +152,7 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s * * \param arm11 Target state variable. * \param chain Scan chain that will be selected. - * \param state Pass the final TAP state or -1 for the default + * \param state Pass the final TAP state or TAP_INVALID for the default * value (Pause-DR). * * The chain takes effect when Update-DR is passed (usually when subsequently @@ -171,7 +171,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) { JTAG_DEBUG("SCREG <= 0x%02x", chain); - arm11_add_IR(arm11, ARM11_SCAN_N, -1); + arm11_add_IR(arm11, ARM11_SCAN_N, TAP_INVALID); scan_field_t field; @@ -179,7 +179,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) field.in_handler = arm11_in_handler_SCAN_N; - arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state); + arm11_add_dr_scan_vc(1, &field, state == TAP_INVALID ? TAP_DRPAUSE : state); } /** Write an instruction into the ITR register @@ -188,7 +188,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) * \param inst An ARM11 processor instruction/opcode. * \param flag Optional parameter to retrieve the InstCompl flag * (this will be written when the JTAG chain is executed). - * \param state Pass the final TAP state or -1 for the default + * \param state Pass the final TAP state or TAP_INVALID for the default * value (Run-Test/Idle). * * \remarks By default this ends with Run-Test/Idle state @@ -208,7 +208,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state); + arm11_add_dr_scan_vc(asizeof(itr), itr, state == TAP_INVALID ? TAP_IDLE : state); } /** Read the Debug Status and Control Register (DSCR) @@ -222,9 +222,9 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state */ u32 arm11_read_DSCR(arm11_common_t * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x01, -1); + arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID); - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); u32 dscr; scan_field_t chain1_field; @@ -254,9 +254,9 @@ u32 arm11_read_DSCR(arm11_common_t * arm11) */ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) { - arm11_add_debug_SCAN_N(arm11, 0x01, -1); + arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID); scan_field_t chain1_field; @@ -331,7 +331,7 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) */ void arm11_run_instr_data_prepare(arm11_common_t * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID); } /** Cleanup after ITR/DTR operations @@ -350,7 +350,7 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11) */ void arm11_run_instr_data_finish(arm11_common_t * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x00, -1); + arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID); } @@ -365,7 +365,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) */ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID); while (count--) { @@ -414,11 +414,11 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) */ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID); arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID); scan_field_t chain5_fields[3]; @@ -446,7 +446,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data data++; } - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); do { @@ -495,11 +495,11 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = */ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID); arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID); scan_field_t chain5_fields[3]; @@ -527,7 +527,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 } } - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); chain5_fields[0].out_value = 0; chain5_fields[1].in_value = ReadyPos++; @@ -584,11 +584,11 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) */ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID); arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE); - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID); scan_field_t chain5_fields[3]; @@ -666,9 +666,9 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 */ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) { - arm11_add_debug_SCAN_N(arm11, 0x07, -1); + arm11_add_debug_SCAN_N(arm11, 0x07, TAP_INVALID); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID); scan_field_t chain7_fields[3]; diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 12c20943..99eede20 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -136,10 +136,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); if (clock) - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ if((retval = jtag_execute_queue()) != ERROR_OK) diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 41b4181a..0c408a7a 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -169,9 +169,9 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int 2, arm7tdmi_num_bits, values, - -1); + TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); return ERROR_OK; } @@ -219,9 +219,9 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { @@ -291,9 +291,9 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 5003445a..29f5b15d 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -150,12 +150,12 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); fields[1].in_handler_priv = value; fields[1].in_handler = arm_jtag_buf_to_u32; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ jtag_execute_queue(); @@ -222,7 +222,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); @@ -289,7 +289,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index ee8bcbc9..ba156d48 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -178,7 +178,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); fields[0].in_handler_priv = value; fields[0].in_handler = arm_jtag_buf_to_u32; @@ -189,7 +189,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -268,14 +268,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); /*TODO: add timeout*/ do { /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 50599fd1..dbe70735 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -214,12 +214,12 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); fields[0].in_handler_priv = value; fields[0].in_handler = arm_jtag_buf_to_u32; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ if((retval = jtag_execute_queue()) != ERROR_OK) @@ -282,7 +282,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 340c5beb..15ce8dcb 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -253,9 +253,9 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { @@ -320,9 +320,9 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { @@ -403,9 +403,9 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, TAP_INVALID); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c index 888d0f7f..cfb85a44 100644 --- a/src/target/arm_jtag.c +++ b/src/target/arm_jtag.c @@ -58,7 +58,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, in_handler_t handl field.in_check_mask = NULL; field.in_handler = handler; field.in_handler_priv = NULL; - jtag_add_ir_scan(1, &field, -1); + jtag_add_ir_scan(1, &field, TAP_INVALID); } return ERROR_OK; @@ -84,7 +84,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain) 1, num_bits, values, - -1); + TAP_INVALID); jtag_info->cur_scan_chain = new_scan_chain; } diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index 84be9171..98037c09 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -91,7 +91,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); return ERROR_OK; } @@ -136,7 +136,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); return ERROR_OK; } diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 05c80f8b..aa9e8f9a 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -283,7 +283,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); fields[0].in_value = reg->value; jtag_set_check_value(fields+0, check_value, check_mask, NULL); @@ -294,7 +294,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) */ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); return ERROR_OK; } @@ -345,7 +345,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); while (size > 0) { @@ -357,7 +357,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = data; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); data++; size--; @@ -465,7 +465,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) while (size > 0) { buf_set_u32(fields[0].out_value, 0, 32, *data); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); data++; size--; @@ -531,11 +531,11 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); gettimeofday(&lap, NULL); do { - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index f9ac2fd4..a0483d36 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -124,7 +124,7 @@ static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_add 3, embeddedice_num_bits, values, - -1); + TAP_INVALID); } void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count); diff --git a/src/target/etb.c b/src/target/etb.c index cfaf1cdc..9fa1f03c 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -82,7 +82,7 @@ int etb_set_instr(etb_t *etb, u32 new_instr) field.in_handler = NULL; field.in_handler_priv = NULL; - jtag_add_ir_scan(1, &field, -1); + jtag_add_ir_scan(1, &field, TAP_INVALID); free(field.out_value); } @@ -109,7 +109,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain) /* select INTEST instruction */ etb_set_instr(etb, 0x2); - jtag_add_dr_scan(1, &field, -1); + jtag_add_dr_scan(1, &field, TAP_INVALID); etb->cur_scan_chain = new_scan_chain; @@ -220,7 +220,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); fields[0].in_handler = buf_to_u32_handler; @@ -236,7 +236,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames) buf_set_u32(fields[1].out_value, 0, 7, 0); fields[0].in_handler_priv = &data[i]; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); } jtag_execute_queue(); @@ -291,7 +291,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); /* read the identification register in the second run, to make sure we * don't read the ETB data register twice, skipping every second entry @@ -301,7 +301,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) jtag_set_check_value(fields+0, check_value, check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); free(fields[1].out_value); free(fields[2].out_value); @@ -388,7 +388,7 @@ int etb_write_reg(reg_t *reg, u32 value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); free(fields[0].out_value); free(fields[1].out_value); diff --git a/src/target/etm.c b/src/target/etm.c index e0aac07f..2e422ee6 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -371,12 +371,12 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); fields[0].in_value = reg->value; jtag_set_check_value(fields+0, check_value, check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); free(fields[1].out_value); free(fields[2].out_value); @@ -463,7 +463,7 @@ int etm_write_reg(reg_t *reg, u32 value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); free(fields[0].out_value); free(fields[1].out_value); @@ -883,7 +883,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx) continue; /* indirect branch to the exception vector means an exception occured */ - if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20)) + if ((ctx->last_branch <= 0x20) || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020))) { if ((ctx->last_branch & 0xff) == 0x10) diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 08512a4b..c4fe17b2 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -162,9 +162,9 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); - /* no jtag_add_runtest(0, -1) here */ + /* no jtag_add_runtest(0, TAP_INVALID) here */ return ERROR_OK; } diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index c1df67b1..cbd30f98 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -55,7 +55,7 @@ int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t h field.in_check_mask = NULL; field.in_handler = handler; field.in_handler_priv = NULL; - jtag_add_ir_scan(1, &field, -1); + jtag_add_ir_scan(1, &field, TAP_INVALID); } return ERROR_OK; @@ -78,7 +78,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha field.in_check_mask = NULL; field.in_handler = NULL; field.in_handler_priv = NULL; - jtag_add_dr_scan(1, &field, -1); + jtag_add_dr_scan(1, &field, TAP_INVALID); if (jtag_execute_queue() != ERROR_OK) { @@ -105,7 +105,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t field.in_check_mask = NULL; field.in_handler = NULL; field.in_handler_priv = NULL; - jtag_add_dr_scan(1, &field, -1); + jtag_add_dr_scan(1, &field, TAP_INVALID); if (jtag_execute_queue() != ERROR_OK) { @@ -136,7 +136,7 @@ int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data) field.in_check_mask = NULL; field.in_handler = NULL; field.in_handler_priv = NULL; - jtag_add_dr_scan(1, &field, -1); + jtag_add_dr_scan(1, &field, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) { diff --git a/src/target/xscale.c b/src/target/xscale.c index a11ed71b..007bdbd6 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -229,7 +229,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr) field.in_value = NULL; jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL); - jtag_add_ir_scan(1, &field, -1); + jtag_add_ir_scan(1, &field, TAP_INVALID); free(field.out_value); } @@ -282,7 +282,7 @@ int xscale_read_dcsr(target_t *target) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -302,7 +302,7 @@ int xscale_read_dcsr(target_t *target) jtag_add_end_state(TAP_IDLE); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); /* DANGER!!! this must be here. It will make sure that the arguments * to jtag_set_check_value() does not go out of scope! */ @@ -362,7 +362,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ + jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ int attempts=0; @@ -750,7 +750,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -822,7 +822,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); fields[0].num_bits = 32; fields[0].out_value = packet; @@ -834,7 +834,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) { buf_set_u32(packet, 0, 32, buffer[word]); cmd = parity(*((u32*)packet)); - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); } jtag_execute_queue(); @@ -880,7 +880,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); return ERROR_OK; } -- cgit v1.2.3