From d86100261252805215282b17d214c48021ef7f79 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 4 Jun 2009 13:18:07 +0000 Subject: Rename jtag_add_end_state to jtag_set_end_state since "add" implies that this fn has something to do with the queue, which it does not as such. git-svn-id: svn://svn.berlios.de/openocd/trunk@2050 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm11_dbgtap.c | 6 +++--- src/target/arm720t.c | 2 +- src/target/arm7_9_common.c | 8 ++++---- src/target/arm7tdmi.c | 12 ++++++------ src/target/arm920t.c | 6 +++--- src/target/arm926ejs.c | 4 ++-- src/target/arm966e.c | 4 ++-- src/target/arm9tdmi.c | 12 ++++++------ src/target/arm_adi_v5.c | 8 ++++---- src/target/avrt.c | 4 ++-- src/target/embeddedice.c | 10 +++++----- src/target/etb.c | 6 +++--- src/target/etm.c | 4 ++-- src/target/feroceon.c | 2 +- src/target/mips_ejtag.c | 6 +++--- src/target/mips_m4k.c | 10 +++++----- src/target/xscale.c | 34 +++++++++++++++++----------------- 17 files changed, 69 insertions(+), 69 deletions(-) (limited to 'src/target') diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 06b002de..6c476b1d 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -439,7 +439,7 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, { Data = *data; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_add_end_state(TAP_IDLE)); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); CHECK_RETVAL(jtag_execute_queue()); @@ -526,13 +526,13 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * if (count) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_add_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE)); jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); } else { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_add_end_state(TAP_IDLE)); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); } } diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 24eee6c6..ef7ad921 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -96,7 +96,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 7e9a3185..9ec3e6c8 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -693,7 +693,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -747,7 +747,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -1724,14 +1724,14 @@ int arm7_9_restart_core(struct target_s *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); } arm_jtag_set_instr(jtag_info, 0x4, NULL); - jtag_add_runtest(1, jtag_add_end_state(TAP_IDLE)); + jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE)); return jtag_execute_queue(); } diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 28bfb154..0c4094ed 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -98,7 +98,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) u8 databus[4]; u8 breakpoint; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; @@ -116,7 +116,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -127,7 +127,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[1].in_value = NULL; fields[1].out_value = databus; - jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); if (breakpoint & 1) target->debug_reason = DBG_REASON_WATCHPOINT; @@ -157,7 +157,7 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) { - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -170,7 +170,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; @@ -260,7 +260,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 22300115..049e5d18 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -103,7 +103,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 0; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -156,7 +156,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -201,7 +201,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) u8 nr_w_buf = 0; u8 cp15_opcode_buf[4]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 1c5b1256..e7309786 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -129,7 +129,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 buf_set_u32(address_buf, 0, 14, address); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -200,7 +200,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 269b7138..e8ced34e 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -167,7 +167,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 0; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -222,7 +222,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 06f9fa31..f569ab31 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -111,7 +111,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) u8 instructionbus[4]; u8 debug_reason; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 32; @@ -134,7 +134,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -147,7 +147,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[2].in_value = NULL; fields[2].out_value = instructionbus; - jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); if (debug_reason & 0x4) if (debug_reason & 0x2) @@ -178,7 +178,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; @@ -240,7 +240,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) int retval = ERROR_OK;; scan_field_t fields[3]; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; @@ -307,7 +307,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int retval = ERROR_OK; scan_field_t fields[3]; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 7dc5aa1f..251f2581 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -65,12 +65,12 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o scan_field_t fields[2]; u8 out_addr_buf; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_add_end_state(TAP_IDLE)); + jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; @@ -96,12 +96,12 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u u8 out_value_buf[4]; u8 out_addr_buf; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_add_end_state(TAP_IDLE)); + jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; diff --git a/src/target/avrt.c b/src/target/avrt.c index e0f1d3c7..373f6b9f 100644 --- a/src/target/avrt.c +++ b/src/target/avrt.c @@ -218,7 +218,7 @@ int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti) field[0].num_bits = tap->ir_length; field[0].out_value = ir_out; field[0].in_value = ir_in; - jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, jtag_add_end_state(TAP_IDLE)); + jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, jtag_set_end_state(TAP_IDLE)); } return ERROR_OK; @@ -239,7 +239,7 @@ int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti) field[0].num_bits = dr_len; field[0].out_value = dr_out; field[0].in_value = dr_in; - jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, jtag_add_end_state(TAP_IDLE)); + jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, jtag_set_end_state(TAP_IDLE)); } return ERROR_OK; diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 96b653e2..b61df8b0 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -238,7 +238,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); @@ -293,7 +293,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -369,7 +369,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); @@ -395,7 +395,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -450,7 +450,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) else return ERROR_INVALID_ARGUMENTS; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); diff --git a/src/target/etb.c b/src/target/etb.c index 31517d7a..d1c60a74 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -169,7 +169,7 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames) scan_field_t fields[3]; int i; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); etb_scann(etb, 0x0); etb_set_instr(etb, 0xc); @@ -225,7 +225,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) LOG_DEBUG("%i", etb_reg->addr); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); @@ -314,7 +314,7 @@ int etb_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); diff --git a/src/target/etm.c b/src/target/etm.c index 22b50d76..d15342dc 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -320,7 +320,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) LOG_DEBUG("%i", etm_reg->addr); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); @@ -405,7 +405,7 @@ int etm_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 36c738f7..f0407f7d 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -124,7 +124,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index f9a6862e..2394b00c 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -60,7 +60,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode) { scan_field_t field; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL); @@ -87,7 +87,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode) { scan_field_t field; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL); @@ -199,7 +199,7 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step) int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info) { u32 ejtag_ctrl; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); /* set debug break bit */ diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 078e2956..d69a0a0a 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -161,7 +161,7 @@ int mips_m4k_poll(target_t *target) u32 ejtag_ctrl = ejtag_info->ejtag_ctrl; /* read ejtag control reg */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); @@ -171,7 +171,7 @@ int mips_m4k_poll(target_t *target) { /* we have detected a reset, clear flag * otherwise ejtag will not work */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -184,7 +184,7 @@ int mips_m4k_poll(target_t *target) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); target->state = TARGET_HALTED; @@ -276,12 +276,12 @@ int mips_m4k_assert_reset(target_t *target) if (target->reset_halt) { /* use hardware to catch reset */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); } else { - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); } diff --git a/src/target/xscale.c b/src/target/xscale.c index fa9bb70b..c571274a 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -238,7 +238,7 @@ int xscale_read_dcsr(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -283,7 +283,7 @@ int xscale_read_dcsr(target_t *target) fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -345,7 +345,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[2].check_value = &field2_check_value; fields[2].check_mask = &field2_check_mask; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ @@ -363,7 +363,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_value = (u8 *)(field1+i); - jtag_add_dr_scan_check(3, fields, jtag_add_end_state(TAP_IDLE)); + jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE)); jtag_add_callback(xscale_getbuf, (u8 *)(field1+i)); @@ -429,7 +429,7 @@ int xscale_read_tx(target_t *target, int consume) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); @@ -477,7 +477,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); } - jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_IDLE)); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); @@ -532,7 +532,7 @@ int xscale_write_rx(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -560,7 +560,7 @@ int xscale_write_rx(target_t *target) LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_IDLE)); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); @@ -592,7 +592,7 @@ int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_IDLE)); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -615,7 +615,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) int done_count = 0; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -658,7 +658,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) 3, bits, t, - jtag_add_end_state(TAP_IDLE)); + jtag_set_end_state(TAP_IDLE)); buffer += size; } @@ -701,7 +701,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if (ext_dbg_brk != -1) xscale->external_debug_break = ext_dbg_brk; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -766,7 +766,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) LOG_DEBUG("loading miniIC at 0x%8.8x", va); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD is b010 for Main IC and b011 for Mini IC */ @@ -833,7 +833,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) scan_field_t fields[2]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD for invalidate IC line b000, bits [6:4] b000 */ @@ -1572,7 +1572,7 @@ int xscale_assert_reset(target_t *target) /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); /* set Hold reset, Halt mode and Trap Reset */ @@ -1646,7 +1646,7 @@ int xscale_deassert_reset(target_t *target) /* wait 300ms; 150 and 100ms were not enough */ jtag_add_sleep(300*1000); - jtag_add_runtest(2030, jtag_add_end_state(TAP_IDLE)); + jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE)); jtag_execute_queue(); /* set Hold reset, Halt mode and Trap Reset */ @@ -1709,7 +1709,7 @@ int xscale_deassert_reset(target_t *target) xscale_load_ic(target, 1, 0x0, xscale->low_vectors); xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); - jtag_add_runtest(30, jtag_add_end_state(TAP_IDLE)); + jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); jtag_add_sleep(100000); -- cgit v1.2.3