From f8c97a5d2e15c630479406cf5cc6a6e384336110 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Sun, 1 Mar 2009 21:00:07 +0000
Subject: Nicolas Pitre nico at cam.org add Feroceon target config file

git-svn-id: svn://svn.berlios.de/openocd/trunk@1389 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/target/feroceon.c          |  2 +-
 src/target/target/feroceon.cfg | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 src/target/target/feroceon.cfg

(limited to 'src/target')

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index b0c4069e..df0feb0d 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -22,7 +22,7 @@
  ***************************************************************************/
 
 /*
- * Marvell Feroceon (88F5182, 88F5281) support.
+ * Marvell Feroceon support, including Orion and Kirkwood SOCs.
  *
  * The Feroceon core mimics the ARM926 ICE interface with the following
  * differences:
diff --git a/src/target/target/feroceon.cfg b/src/target/target/feroceon.cfg
new file mode 100644
index 00000000..26f63f2f
--- /dev/null
+++ b/src/target/target/feroceon.cfg
@@ -0,0 +1,30 @@
+######################################
+# Target:    Marvell Feroceon CPU core
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME feroceon
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x20a023d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
-- 
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