From 71af49ca7fb11b0bd0c1ba9578826f49288b68ef Mon Sep 17 00:00:00 2001
From: dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Mon, 21 Sep 2009 18:48:22 +0000
Subject: Remove annoying end-of-line whitespace from tcl/* files

git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 tcl/board/csb732.cfg | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'tcl/board/csb732.cfg')

diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 8bf77cb3..17873230 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -11,7 +11,7 @@ $_TARGETNAME configure -event reset-init { csb732_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc csb732_init { } {
-	
+
 	# Disable fast writing only for init
 	memwrite burst disable
 
@@ -29,17 +29,17 @@ proc csb732_init { } {
 
 	# Set ARM clock to 532 MHz, AHB to 133 MHz
 	mww 0x53F80004 0x1000
-	
+
 	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
 	mww 0x53F8001C 0xB2C01
-	
+
 	set ESDMISC 0xB8001010
 	set ESDCFG0 0xB8001004
 	set ESDCTL0 0xB8001000
 
 	# Enable DDR
 	mww $ESDMISC 0x4
-	
+
 	# Timing
 	mww $ESDCFG0 0x007fff3f
 
@@ -51,7 +51,7 @@ proc csb732_init { } {
 
 	# Enable CS) auto-refresh
 	mww $ESDCTL0 0xA2120080
-	
+
 	# Refresh twice (dummy writes)
 	mww 0x80000000 0
 	mww 0x80000000 0
@@ -59,7 +59,7 @@ proc csb732_init { } {
 	# Enable CS0 load mode register
 	mww $ESDCTL0 0xB2120080
 
-	# Dummy writes	
+	# Dummy writes
 	mwb 0x80000033 0x01
 	mwb 0x81000000 0x01
 
-- 
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