From 2c4ef30b11f459028c20185f41320e856db8c3a1 Mon Sep 17 00:00:00 2001
From: Øyvind Harboe <oyvind.harboe@zylin.com>
Date: Tue, 17 Aug 2010 21:51:36 +0200
Subject: mcb1700: Keil MCB1700 w/1768 config script
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Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 tcl/board/mcb1700.cfg | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 tcl/board/mcb1700.cfg

(limited to 'tcl/board')

diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
new file mode 100644
index 00000000..845c7e20
--- /dev/null
+++ b/tcl/board/mcb1700.cfg
@@ -0,0 +1,75 @@
+# Keil MCB1700 PCB with 1768
+# 
+# Reset init script sets it to 100MHz
+set CCLK 100000
+
+source [find target/lpc1768.cfg] 
+
+global MCB1700_CCLK
+set MCB1700_CCLK $CCLK
+
+$_TARGETNAME configure -event reset-start {
+	# Start *real slow* as we do not know the
+    # state the boot rom left the clock in
+	jtag_khz 10
+}
+
+# Set up 100MHz clock to CPU
+$_TARGETNAME configure -event reset-init {
+    # PLL0CON: Disable PLL
+	mww 0x400FC080 0x00000000
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+    # CCLK=PLL/4 (=100 MHz)
+	mww 0x400FC104 0x00000003
+    # CLKSRCSEL: Clock source = internal RC oscillator
+	mww 0x400FC10C 0x00000000
+
+    # PLL0CFG: M=50,N=1 -> PLL=400 MHz
+	mww 0x400FC084 0x00000031
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# PLL0CON: Enable PLL
+	mww 0x400FC080 0x00000001
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	sleep 50
+
+    # PLL0CON: Connect PLL
+	mww 0x400FC080 0x00000003
+    # PLLFEED
+	mww 0x400FC08C 0x000000AA
+    # PLLFEED
+	mww 0x400FC08C 0x00000055
+
+	# Dividing CPU clock by 8 should be pretty conservative
+	#
+	# 
+	global MCB1700_CCLK
+	jtag_khz [expr $MCB1700_CCLK / 8]
+
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+	mww 0x400FC040 0x01
+}
-- 
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