From 30da7c67cec8b315972377b5389735ff11f6042c Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 19 Dec 2010 01:22:53 +0800 Subject: TCL: fix non TCL comments End of line comments fixed with ';' before '#'. Added few additional 'space' to keep indentation in multi-line comments. Signed-off-by: Antonio Borneo --- tcl/target/ar71xx.cfg | 42 ++++++++++---------- tcl/target/at91sam9260_ext_RAM_ext_flash.cfg | 58 ++++++++++++++-------------- tcl/target/lpc3131.cfg | 2 +- tcl/target/xba_revA3.cfg | 48 +++++++++++------------ 4 files changed, 75 insertions(+), 75 deletions(-) (limited to 'tcl/target') diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 126efe4d..3ac61d94 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -15,35 +15,35 @@ target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME $TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting - mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0 - mww 0xb8050000 0x800f40a3 # send to PLL + mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 + mww 0xb8050000 0x800f40a3 ;# send to PLL #next command will reset for PLL changes to take effect - mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC) + mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) } $TARGETNAME configure -event reset-init { #complete pll initialization - mww 0xb8050000 0x800f0080 # set sw_update bit - mww 0xb8050008 0 # clear reset_switch bit - mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass - mww 0xb8050008 1 # set clock_switch bit - sleep 1 # wait for lock + mww 0xb8050000 0x800f0080 ;# set sw_update bit + mww 0xb8050008 0 ;# clear reset_switch bit + mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass + mww 0xb8050008 1 ;# set clock_switch bit + sleep 1 ;# wait for lock # Setup DDR config and flash mapping - mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0) - mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8) - - mww 0xb8000010 8 # force precharge all banks - mww 0xb8000010 1 # force EMRS update cycle - mww 0xb800000c 0 # clr ext. mode register - mww 0xb8000010 2 # force auto refresh all banks - mww 0xb8000010 8 # force precharge all banks - mww 0xb8000008 0x31 # set DDR mode value CAS=3 - mww 0xb8000010 1 # force EMRS update cycle - mww 0xb8000014 0x461b # DDR refresh value - mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff) - mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7) + mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) + mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8) + + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb800000c 0 ;# clr ext. mode register + mww 0xb8000010 2 ;# force auto refresh all banks + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb8000014 0x461b ;# DDR refresh value + mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) + mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) mww 0xb8000020 0 mww 0xb8000024 0 mww 0xb8000028 0 diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 535ae0fb..8acdebd7 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -63,41 +63,41 @@ arm7_9 dcc_downloads enable arm7_9 fast_memory_access enable proc at91sam_init { } { - mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset - mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog - - mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator - sleep 20 # wait 20 ms - mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator - sleep 10 # wait 10 ms - mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz - sleep 20 # wait 20 ms - mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler - sleep 10 # wait 10 ms - mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected - sleep 10 # wait 10 ms + mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected + sleep 10 ;# wait 10 ms # Now run at anything fast... ie: 10mhz! - jtag_rclk 10000 # Increase JTAG Speed to 6 MHz + jtag_rclk 10000 ;# Increase JTAG Speed to 6 MHz - mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit - mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0 - mww 0xffffec08 0x00160016 # SMC_CYCLE0 - mww 0xffffec0c 0x00161003 # SMC_MODE0 + mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit + mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0 + mww 0xffffec08 0x00160016 ;# SMC_CYCLE0 + mww 0xffffec0c 0x00161003 ;# SMC_MODE0 - mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 - mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 + mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 - mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM + mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM - mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) - #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) + #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) - mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command mww 0x20000000 0 - mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command mww 0x20000000 0 - mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 @@ -113,9 +113,9 @@ proc at91sam_init { } { mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 - mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command mww 0x20000000 0 - mww 0xffffea00 0x0 # SDRAMC_MR : normal mode + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode mww 0x20000000 0 - mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us + mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us } diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg index 5c6aa3ce..560555b4 100644 --- a/tcl/target/lpc3131.cfg +++ b/tcl/target/lpc3131.cfg @@ -66,7 +66,7 @@ $_TARGETNAME configure -event reset-init { echo "\nRunning reset init script for LPC3131\n" halt wait_halt - reg cpsr 0xa00000d3 #Supervisor mode + reg cpsr 0xa00000d3 ;#Supervisor mode reg pc 0x11029000 poll sleep 500 diff --git a/tcl/target/xba_revA3.cfg b/tcl/target/xba_revA3.cfg index 8ff5be93..71e7353d 100644 --- a/tcl/target/xba_revA3.cfg +++ b/tcl/target/xba_revA3.cfg @@ -35,36 +35,36 @@ $_TARGETNAME configure -event reset-init { ############################################################################# # setup expansion bus CS, disable external wdt ############################################################################# - mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000 - mww 0xc4000004 0x94d10013 #CS1 - mww 0xc4000008 0x95960003 #CS2 - mww 0xc400000c 0x00000000 #CS3 - mww 0xc4000010 0x80900003 #CS4 - mww 0xc4000014 0x9d520003 #CS5 - mww 0xc4000018 0x81860001 #CS6 - mww 0xc400001c 0x80900003 #CS7 + mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000 + mww 0xc4000004 0x94d10013 ;#CS1 + mww 0xc4000008 0x95960003 ;#CS2 + mww 0xc400000c 0x00000000 ;#CS3 + mww 0xc4000010 0x80900003 ;#CS4 + mww 0xc4000014 0x9d520003 ;#CS5 + mww 0xc4000018 0x81860001 ;#CS6 + mww 0xc400001c 0x80900003 ;#CS7 ############################################################################# # init SDRAM controller: 16MB, one bank, CL3 ############################################################################# - mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3 - mww 0xCC000004 0 # disable refresh - mww 0xCC000008 3 # NOP + mww 0xCC000000 0x2A ;# SDRAM_CFG: 64MBit, CL3 + mww 0xCC000004 0 ;# disable refresh + mww 0xCC000008 3 ;# NOP sleep 100 - mww 0xCC000004 2100 # set refresh counter - mww 0xCC000008 2 # Precharge All Banks + mww 0xCC000004 2100 ;# set refresh counter + mww 0xCC000008 2 ;# Precharge All Banks sleep 100 - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 4 # Auto Refresh - mww 0xCC000008 1 # Mode Select CL3 - - #mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 1 ;# Mode Select CL3 + + #mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash #mirror at 0x00000000 #big endian -- cgit v1.2.3