From 4a26390eec5b969c07684ab5d4b7e957011d71bd Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 26 Oct 2009 22:59:46 -0700 Subject: PXA255: force reset config These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG. --- tcl/target/pxa255.cfg | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tcl') diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index 7137621a..44efdaa4 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -31,6 +31,10 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \ jtag_khz 300 $_TARGETNAME configure -event "reset-start" { jtag_khz 300 } +# both TRST and SRST are *required* for debug +# DCSR is often accessed with SRST active +reset_config trst_and_srst separate srst_nogate + # reset processing that works with PXA proc init_reset {mode} { # assert both resets; equivalent to power-on reset -- cgit v1.2.3