/*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * * * * Copyright (C) 2008 Georg Acher * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * * (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ #ifndef ARM11_H #define ARM11_H #include "target.h" #include "register.h" #include "embeddedice.h" #include "arm_jtag.h" #include "types.h" #define asizeof(x) (sizeof(x) / sizeof((x)[0])) #define NEW(type, variable, items) \ type * variable = calloc(1, sizeof(type) * items) /* For MinGW use 'I' prefix to print size_t (instead of 'z') */ #ifndef __MSVCRT__ #define ZU "%zu" #else #define ZU "%Iu" #endif #define ARM11_REGCACHE_MODEREGS 0 #define ARM11_REGCACHE_FREGS 0 #define ARM11_REGCACHE_COUNT (20 + \ 23 * ARM11_REGCACHE_MODEREGS + \ 9 * ARM11_REGCACHE_FREGS) #define ARM11_TAP_DEFAULT TAP_INVALID #define CHECK_RETVAL(action) \ do { \ int __retval = (action); \ \ if (__retval != ERROR_OK) \ { \ LOG_DEBUG("error while calling \"" # action "\""); \ return __retval; \ } \ \ } while (0) typedef struct arm11_register_history_s { u32 value; u8 valid; }arm11_register_history_t; enum arm11_debug_version { ARM11_DEBUG_V6 = 0x01, ARM11_DEBUG_V61 = 0x02, ARM11_DEBUG_V7 = 0x03, ARM11_DEBUG_V7_CP14 = 0x04, }; typedef struct arm11_common_s { target_t * target; /**< Reference back to the owner */ arm_jtag_t jtag_info; /**< Handler to access assigned JTAG device */ /** \name Processor type detection */ /*@{*/ u32 device_id; /**< IDCODE readout */ u32 didr; /**< DIDR readout (debug capabilities) */ u8 implementor; /**< DIDR Implementor readout */ size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ enum arm11_debug_version debug_version; /**< ARM debug architecture from DIDR */ /*@}*/ u32 last_dscr; /**< Last retrieved DSCR value; Use only for debug message generation */ bool trst_active; bool halt_requested; /**< Keep track if arm11_halt() calls occured during reset. Otherwise do it ASAP. */ bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ /** \name Shadow registers to save processor state */ /*@{*/ reg_t * reg_list; /**< target register list */ u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */ /*@}*/ arm11_register_history_t reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */ // GA reg_cache_t *core_cache; } arm11_common_t; /** * ARM11 DBGTAP instructions * * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html */ enum arm11_instructions { ARM11_EXTEST = 0x00, ARM11_SCAN_N = 0x02, ARM11_RESTART = 0x04, ARM11_HALT = 0x08, ARM11_INTEST = 0x0C, ARM11_ITRSEL = 0x1D, ARM11_IDCODE = 0x1E, ARM11_BYPASS = 0x1F, }; enum arm11_dscr { ARM11_DSCR_CORE_HALTED = 1 << 0, ARM11_DSCR_CORE_RESTARTED = 1 << 1, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, ARM11_DSCR_MODE_SELECT = 1 << 14, ARM11_DSCR_WDTR_FULL = 1 << 29, ARM11_DSCR_RDTR_FULL = 1 << 30, }; enum arm11_cpsr { ARM11_CPSR_T = 1 << 5, ARM11_CPSR_J = 1 << 24, }; enum arm11_sc7 { ARM11_SC7_NULL = 0, ARM11_SC7_VCR = 7, ARM11_SC7_PC = 8, ARM11_SC7_BVR0 = 64, ARM11_SC7_BCR0 = 80, ARM11_SC7_WVR0 = 96, ARM11_SC7_WCR0 = 112, }; typedef struct arm11_reg_state_s { u32 def_index; target_t * target; } arm11_reg_state_t; /* poll current target status */ int arm11_poll(struct target_s *target); /* architecture specific status reply */ int arm11_arch_state(struct target_s *target); /* target request support */ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer); /* target execution control */ int arm11_halt(struct target_s *target); int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints); int arm11_examine(struct target_s *target); /* target reset control */ int arm11_assert_reset(struct target_s *target); int arm11_deassert_reset(struct target_s *target); int arm11_soft_reset_halt(struct target_s *target); /* target register access for gdb */ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size); /* target memory access * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of */ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer); int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); /* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); /* target algorithm support */ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); int arm11_register_commands(struct command_context_s *cmd_ctx); int arm11_target_create(struct target_s *target, Jim_Interp *interp); int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm11_quit(void); /* helpers */ int arm11_build_reg_cache(target_t *target); int arm11_set_reg(reg_t *reg, u8 *buf); int arm11_get_reg(reg_t *reg); void arm11_record_register_history(arm11_common_t * arm11); void arm11_dump_reg_changes(arm11_common_t * arm11); /* internals */ void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field); void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state); void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state); void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state); int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr); int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr); enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr); void arm11_run_instr_data_prepare (arm11_common_t * arm11); void arm11_run_instr_data_finish (arm11_common_t * arm11); int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count); void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode); int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count); int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count); int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data); int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count); void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data); void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data); int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state); int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state); /** Used to make a list of read/write commands for scan chain 7 * * Use with arm11_sc7_run() */ typedef struct arm11_sc7_action_s { bool write; /**< Access mode: true for write, false for read. */ u8 address; /**< Register address mode. Use enum #arm11_sc7 */ u32 value; /**< If write then set this to value to be written. In read mode this receives the read value when the function returns. */ } arm11_sc7_action_t; int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count); /* Mid-level helper functions */ void arm11_sc7_clear_vbw(arm11_common_t * arm11); void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value); int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result); #endif /* ARM11_H */ ref='#n216'>216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145