/***************************************************************************
 *   Copyright (C) 2006 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
 *   Copyright (C) 2009 by David Brownell                                  *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "target.h"
#include "arm_disassembler.h"
#include "log.h"


/*
 * This disassembler supports two main functions for OpenOCD:
 *
 *  - Various "disassemble" commands.  OpenOCD can serve as a
 *    machine-language debugger, without help from GDB.
 *
 *  - Single stepping.  Not all ARM cores support hardware single
 *    stepping.  To work without that support, the debugger must
 *    be able to decode instructions to find out where to put a
 *    "next instruction" breakpoint.
 *
 * In addition, interpretation of ETM trace data needs some of the
 * decoding mechanisms.
 *
 * At this writing (September 2009) neither function is complete.
 *
 *  - ARM decoding
 *     * Old-style syntax (not UAL) is generally used
 *     * VFP instructions are not understood (ARMv5 and later)
 *       except as coprocessor 10/11 operations
 *     * Most ARM instructions through ARMv6 are decoded, but some
 *       of the post-ARMv4 opcodes may not be handled yet
 *     * NEON instructions are not understood (ARMv7-A)
 *
 *  - Thumb/Thumb2 decoding
 *     * UAL syntax should be consistently used
 *     * Any Thumb2 instructions used in Cortex-M3 (ARMv7-M) should
 *       be handled properly.  Accordingly, so should the subset
 *       used in Cortex-M0/M1; and "original" 16-bit Thumb from
 *       ARMv4T and ARMv5T.
 *     * Conditional effects of Thumb2 "IT" (if-then) instructions
 *       are not handled:  the affected instructions are not shown
 *       with their now-conditional suffixes.
 *     * Some ARMv6 and ARMv7-M Thumb2 instructions may not be
 *       handled (minimally for coprocessor access).
 *     * SIMD instructions, and some other Thumb2 instructions
 *       from ARMv7-A, are not understood.
 *
 *  - ThumbEE decoding
 *     * As a Thumb2 variant, the Thumb2 comments (above) apply.
 *     * Opcodes changed by ThumbEE mode are not handled; these
 *       instructions wrongly decode as LDM and STM.
 *
 *  - Jazelle decoding ...  no support whatsoever for Jazelle mode
 *    or decoding.  ARM encourages use of the more generic ThumbEE
 *    mode, instead of Jazelle mode, in current chips.
 *
 *  - Single-step/emulation ... spotty support, which is only weakly
 *    tested.  Thumb2 is not supported.  (Arguably a full simulator
 *    is not needed to support just single stepping.  Recognizing
 *    branch vs non-branch instructions suffices, except when the
 *    instruction faults and triggers a synchronous exception which
 *    can be intercepted using other means.)
 *
 * ARM DDI 0406B "ARM Architecture Reference Manual, ARM v7-A and
 * ARM v7-R edition" gives the most complete coverage of the various
 * generations of ARM instructions.  At this writing it is publicly
 * accessible to anyone willing to create an account at the ARM
 * web site; see http://www.arm.com/documentation/ for information.
 *
 * ARM DDI 0403C "ARMv7-M Architecture Reference Manual" provides
 * more details relevant to the Thumb2-only processors (such as
 * the Cortex-M implementations).
 */

/* textual represenation of the condition field */
/* ALways (default) is ommitted (empty string) */
static const char *arm_condition_strings[] =
{
	"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV"
};

/* make up for C's missing ROR */
static uint32_t ror(uint32_t value, int places)
{
	return (value >> places) | (value << (32 - places));
}

static int evaluate_pld(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	/* PLD */
	if ((opcode & 0x0d70f000) == 0x0550f000)
	{
		instruction->type = ARM_PLD;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", address, opcode);

		return ERROR_OK;
	}
	else
	{
		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		return ERROR_OK;
	}

	LOG_ERROR("should never reach this point");
	return -1;
}

static int evaluate_swi(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	instruction->type = ARM_SWI;

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSVC %#6.6" PRIx32,
			address, opcode, (opcode & 0xffffff));

	return ERROR_OK;
}

static int evaluate_blx_imm(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	int offset;
	uint32_t immediate;
	uint32_t target_address;

	instruction->type = ARM_BLX;
	immediate = opcode & 0x00ffffff;

	/* sign extend 24-bit immediate */
	if (immediate & 0x00800000)
		offset = 0xff000000 | immediate;
	else
		offset = immediate;

	/* shift two bits left */
	offset <<= 2;

	/* odd/event halfword */
	if (opcode & 0x01000000)
		offset |= 0x2;

	target_address = address + 8 + offset;

	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", address, opcode, target_address);

	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = target_address;

	return ERROR_OK;
}

static int evaluate_b_bl(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t L;
	uint32_t immediate;
	int offset;
	uint32_t target_address;

	immediate = opcode & 0x00ffffff;
	L = (opcode & 0x01000000) >> 24;

	/* sign extend 24-bit immediate */
	if (immediate & 0x00800000)
		offset = 0xff000000 | immediate;
	else
		offset = immediate;

	/* shift two bits left */
	offset <<= 2;

	target_address = address + 8 + offset;

	if (L)
		instruction->type = ARM_BL;
	else
		instruction->type = ARM_B;

	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32 , address, opcode,
			 (L) ? "L" : "", COND(opcode), target_address);

	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = target_address;

	return ERROR_OK;
}

/* Coprocessor load/store and double register transfers */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t cp_num = (opcode & 0xf00) >> 8;

	/* MCRR or MRRC */
	if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000))
	{
		uint8_t cp_opcode, Rd, Rn, CRm;
		char *mnemonic;

		cp_opcode = (opcode & 0xf0) >> 4;
		Rd = (opcode & 0xf000) >> 12;
		Rn = (opcode & 0xf0000) >> 16;
		CRm = (opcode & 0xf);

		/* MCRR */
		if ((opcode & 0x0ff00000) == 0x0c400000)
		{
			instruction->type = ARM_MCRR;
			mnemonic = "MCRR";
		}

		/* MRRC */
		if ((opcode & 0x0ff00000) == 0x0c500000)
		{
			instruction->type = ARM_MRRC;
			mnemonic = "MRRC";
		}

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i",
				 address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
	}
	else /* LDC or STC */
	{
		uint8_t CRd, Rn, offset;
		uint8_t U, N;
		char *mnemonic;
		char addressing_mode[32];

		CRd = (opcode & 0xf000) >> 12;
		Rn = (opcode & 0xf0000) >> 16;
		offset = (opcode & 0xff);

		/* load/store */
		if (opcode & 0x00100000)
		{
			instruction->type = ARM_LDC;
			mnemonic = "LDC";
		}
		else
		{
			instruction->type = ARM_STC;
			mnemonic = "STC";
		}

		U = (opcode & 0x00800000) >> 23;
		N = (opcode & 0x00400000) >> 22;

		/* addressing modes */
		if ((opcode & 0x01200000) == 0x01000000) /* immediate offset */
			snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]", Rn, (U) ? "" : "-", offset);
		else if ((opcode & 0x01200000) == 0x01200000) /* immediate pre-indexed */
			snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]!", Rn, (U) ? "" : "-", offset);
		else if ((opcode & 0x01200000) == 0x00200000) /* immediate post-indexed */
			snprintf(addressing_mode, 32, "[r%i], #%s0x%2.2x*4", Rn, (U) ? "" : "-", offset);
		else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */
			snprintf(addressing_mode, 32, "[r%i], #0x%2.2x", Rn, offset);

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, c%i, %s",
				 address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? COND(opcode) : "2",
				 (N) ? "L" : "",
				 cp_num, CRd, addressing_mode);
	}

	return ERROR_OK;
}

/* Coprocessor data processing instructions */
/* Coprocessor register transfer instructions */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_cdp_mcr_mrc(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	const char *cond;
	char* mnemonic;
	uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;

	cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode);
	cp_num = (opcode & 0xf00) >> 8;
	CRd_Rd = (opcode & 0xf000) >> 12;
	CRn = (opcode & 0xf0000) >> 16;
	CRm = (opcode & 0xf);
	opcode_2 = (opcode & 0xe0) >> 5;

	/* CDP or MRC/MCR */
	if (opcode & 0x00000010) /* bit 4 set -> MRC/MCR */
	{
		if (opcode & 0x00100000) /* bit 20 set -> MRC */
		{
			instruction->type = ARM_MRC;
			mnemonic = "MRC";
		}
		else /* bit 20 not set -> MCR */
		{
			instruction->type = ARM_MCR;
			mnemonic = "MCR";
		}

		opcode_1 = (opcode & 0x00e00000) >> 21;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
				 address, opcode, mnemonic, cond,
				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
	}
	else /* bit 4 not set -> CDP */
	{
		instruction->type = ARM_CDP;
		mnemonic = "CDP";

		opcode_1 = (opcode & 0x00f00000) >> 20;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
				 address, opcode, mnemonic, cond,
				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
	}

	return ERROR_OK;
}

/* Load/store instructions */
static int evaluate_load_store(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t I, P, U, B, W, L;
	uint8_t Rn, Rd;
	char *operation; /* "LDR" or "STR" */
	char *suffix; /* "", "B", "T", "BT" */
	char offset[32];

	/* examine flags */
	I = (opcode & 0x02000000) >> 25;
	P = (opcode & 0x01000000) >> 24;
	U = (opcode & 0x00800000) >> 23;
	B = (opcode & 0x00400000) >> 22;
	W = (opcode & 0x00200000) >> 21;
	L = (opcode & 0x00100000) >> 20;

	/* target register */
	Rd = (opcode & 0xf000) >> 12;

	/* base register */
	Rn = (opcode & 0xf0000) >> 16;

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = Rn;
	instruction->info.load_store.U = U;

	/* determine operation */
	if (L)
		operation = "LDR";
	else
		operation = "STR";

	/* determine instruction type and suffix */
	if (B)
	{
		if ((P == 0) && (W == 1))
		{
			if (L)
				instruction->type = ARM_LDRBT;
			else
				instruction->type = ARM_STRBT;
			suffix = "BT";
		}
		else
		{
			if (L)
				instruction->type = ARM_LDRB;
			else
				instruction->type = ARM_STRB;
			suffix = "B";
		}
	}
	else
	{
		if ((P == 0) && (W == 1))
		{
			if (L)
				instruction->type = ARM_LDRT;
			else
				instruction->type = ARM_STRT;
			suffix = "T";
		}
		else
		{
			if (L)
				instruction->type = ARM_LDR;
			else
				instruction->type = ARM_STR;
			suffix = "";
		}
	}

	if (!I) /* #+-<offset_12> */
	{
		uint32_t offset_12 = (opcode & 0xfff);
		if (offset_12)
			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12);
		else
			snprintf(offset, 32, "%s", "");

		instruction->info.load_store.offset_mode = 0;
		instruction->info.load_store.offset.offset = offset_12;
	}
	else /* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */
	{
		uint8_t shift_imm, shift;
		uint8_t Rm;

		shift_imm = (opcode & 0xf80) >> 7;
		shift = (opcode & 0x60) >> 5;
		Rm = (opcode & 0xf);

		/* LSR encodes a shift by 32 bit as 0x0 */
		if ((shift == 0x1) && (shift_imm == 0x0))
			shift_imm = 0x20;

		/* ASR encodes a shift by 32 bit as 0x0 */
		if ((shift == 0x2) && (shift_imm == 0x0))
			shift_imm = 0x20;

		/* ROR by 32 bit is actually a RRX */
		if ((shift == 0x3) && (shift_imm == 0x0))
			shift = 0x4;

		instruction->info.load_store.offset_mode = 1;
		instruction->info.load_store.offset.reg.Rm = Rm;
		instruction->info.load_store.offset.reg.shift = shift;
		instruction->info.load_store.offset.reg.shift_imm = shift_imm;

		if ((shift_imm == 0x0) && (shift == 0x0)) /* +-<Rm> */
		{
			snprintf(offset, 32, ", %sr%i", (U) ? "" : "-", Rm);
		}
		else /* +-<Rm>, <Shift>, #<shift_imm> */
		{
			switch (shift)
			{
				case 0x0: /* LSL */
					snprintf(offset, 32, ", %sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm);
					break;
				case 0x1: /* LSR */
					snprintf(offset, 32, ", %sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm);
					break;
				case 0x2: /* ASR */
					snprintf(offset, 32, ", %sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm);
					break;
				case 0x3: /* ROR */
					snprintf(offset, 32, ", %sr%i, ROR #0x%x", (U) ? "" : "-", Rm, shift_imm);
					break;
				case 0x4: /* RRX */
					snprintf(offset, 32, ", %sr%i, RRX", (U) ? "" : "-", Rm);
					break;
			}
		}
	}

	if (P == 1)
	{
		if (W == 0) /* offset */
		{
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]",
					 address, opcode, operation, COND(opcode), suffix,
					 Rd, Rn, offset);

			instruction->info.load_store.index_mode = 0;
		}
		else /* pre-indexed */
		{
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!",
					 address, opcode, operation, COND(opcode), suffix,
					 Rd, Rn, offset);

			instruction->info.load_store.index_mode = 1;
		}
	}
	else /* post-indexed */
	{
		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s",
				 address, opcode, operation, COND(opcode), suffix,
				 Rd, Rn, offset);

		instruction->info.load_store.index_mode = 2;
	}

	return ERROR_OK;
}

static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
{
	unsigned rm = (opcode >> 0) & 0xf;
	unsigned rd = (opcode >> 12) & 0xf;
	unsigned rn = (opcode >> 16) & 0xf;
	char *type, *rot;

	switch ((opcode >> 24) & 0x3) {
	case 0:
		type = "B16";
		break;
	case 1:
		sprintf(cp, "UNDEFINED");
		return ARM_UNDEFINED_INSTRUCTION;
	case 2:
		type = "B";
		break;
	default:
		type = "H";
		break;
	}

	switch ((opcode >> 10) & 0x3) {
	case 0:
		rot = "";
		break;
	case 1:
		rot = ", ROR #8";
		break;
	case 2:
		rot = ", ROR #16";
		break;
	default:
		rot = ", ROR #24";
		break;
	}

	if (rn == 0xf) {
		sprintf(cp, "%cXT%s%s\tr%d, r%d%s",
				(opcode & (1 << 22)) ? 'U' : 'S',
				type, COND(opcode),
				rd, rm, rot);
		return ARM_MOV;
	} else {
		sprintf(cp, "%cXTA%s%s\tr%d, r%d, r%d%s",
				(opcode & (1 << 22)) ? 'U' : 'S',
				type, COND(opcode),
				rd, rn, rm, rot);
		return ARM_ADD;
	}
}

static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp)
{
	char *prefix;
	char *op;
	int type;

	switch ((opcode >> 20) & 0x7) {
	case 1:
		prefix = "S";
		break;
	case 2:
		prefix = "Q";
		break;
	case 3:
		prefix = "SH";
		break;
	case 5:
		prefix = "U";
		break;
	case 6:
		prefix = "UQ";
		break;
	case 7:
		prefix = "UH";
		break;
	default:
		goto undef;
	}

	switch ((opcode >> 5) & 0x7) {
	case 0:
		op = "ADD16";
		type = ARM_ADD;
		break;
	case 1:
		op = "ADDSUBX";
		type = ARM_ADD;
		break;
	case 2:
		op = "SUBADDX";
		type = ARM_SUB;
		break;
	case 3:
		op = "SUB16";
		type = ARM_SUB;
		break;
	case 4:
		op = "ADD8";
		type = ARM_ADD;
		break;
	case 7:
		op = "SUB8";
		type = ARM_SUB;
		break;
	default:
		goto undef;
	}

	sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf);
	return type;

undef:
	/* these opcodes might be used someday */
	sprintf(cp, "UNDEFINED");
	return ARM_UNDEFINED_INSTRUCTION;
}

/* ARMv6 and later support "media" instructions (includes SIMD) */
static int evaluate_media(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	char *cp = instruction->text;
	char *mnemonic = NULL;

	sprintf(cp,
		"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t",
		address, opcode);
	cp = strchr(cp, 0);

	/* parallel add/subtract */
	if ((opcode & 0x01800000) == 0x00000000) {
		instruction->type = evaluate_p_add_sub(opcode, address, cp);
		return ERROR_OK;
	}

	/* halfword pack */
	if ((opcode & 0x01f00020) == 0x00800000) {
		char *type, *shift;
		unsigned imm = (unsigned) (opcode >> 7) & 0x1f;

		if (opcode & (1 << 6)) {
			type = "TB";
			shift = "ASR";
			if (imm == 0)
				imm = 32;
		} else {
			type = "BT";
			shift = "LSL";
		}
		sprintf(cp, "PKH%s%s\tr%d, r%d, r%d, %s #%d",
			type, COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf,
			shift, imm);
		return ERROR_OK;
	}

	/* word saturate */
	if ((opcode & 0x01a00020) == 0x00a00000) {
		char *shift;
		unsigned imm = (unsigned) (opcode >> 7) & 0x1f;

		if (opcode & (1 << 6)) {
			shift = "ASR";
			if (imm == 0)
				imm = 32;
		} else {
			shift = "LSL";
		}

		sprintf(cp, "%cSAT%s\tr%d, #%d, r%d, %s #%d",
			(opcode & (1 << 22)) ? 'U' : 'S',
			COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0x1f,
			(int) (opcode >> 0) & 0xf,
			shift, imm);
		return ERROR_OK;
	}

	/* sign extension */
	if ((opcode & 0x018000f0) == 0x00800070) {
		instruction->type = evaluate_extend(opcode, address, cp);
		return ERROR_OK;
	}

	/* multiplies */
	if ((opcode & 0x01f00080) == 0x01000000) {
		unsigned rn = (opcode >> 12) & 0xf;

		if (rn != 0xf)
			sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
				(opcode & (1 << 6)) ? 'S' : 'A',
				(opcode & (1 << 5)) ? "X" : "",
				COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf,
				rn);
		else
			sprintf(cp, "SMU%cD%s%s\tr%d, r%d, r%d",
				(opcode & (1 << 6)) ? 'S' : 'A',
				(opcode & (1 << 5)) ? "X" : "",
				COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf);
		return ERROR_OK;
	}
	if ((opcode & 0x01f00000) == 0x01400000) {
		sprintf(cp, "SML%cLD%s%s\tr%d, r%d, r%d, r%d",
			(opcode & (1 << 6)) ? 'S' : 'A',
			(opcode & (1 << 5)) ? "X" : "",
			COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf,
			(int) (opcode >> 8) & 0xf);
		return ERROR_OK;
	}
	if ((opcode & 0x01f00000) == 0x01500000) {
		unsigned rn = (opcode >> 12) & 0xf;

		switch (opcode & 0xc0) {
		case 3:
			if (rn == 0xf)
				goto undef;
			/* FALL THROUGH */
		case 0:
			break;
		default:
			goto undef;
		}

		if (rn != 0xf)
			sprintf(cp, "SMML%c%s%s\tr%d, r%d, r%d, r%d",
				(opcode & (1 << 6)) ? 'S' : 'A',
				(opcode & (1 << 5)) ? "R" : "",
				COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf,
				rn);
		else
			sprintf(cp, "SMMUL%s%s\tr%d, r%d, r%d",
				(opcode & (1 << 5)) ? "R" : "",
				COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf);
		return ERROR_OK;
	}


	/* simple matches against the remaining decode bits */
	switch (opcode & 0x01f000f0) {
	case 0x00a00030:
	case 0x00e00030:
		/* parallel halfword saturate */
		sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d",
			(opcode & (1 << 22)) ? 'U' : 'S',
			COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf);
		return ERROR_OK;
	case 0x00b00030:
		mnemonic = "REV";
		break;
	case 0x00b000b0:
		mnemonic = "REV16";
		break;
	case 0x00f000b0:
		mnemonic = "REVSH";
		break;
	case 0x008000b0:
		/* select bytes */
		sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode),
			(int) (opcode >> 12) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf);
		return ERROR_OK;
	case 0x01800010:
		/* unsigned sum of absolute differences */
		if (((opcode >> 12) & 0xf) == 0xf)
			sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf);
		else
			sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode),
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 12) & 0xf);
		return ERROR_OK;
	}
	if (mnemonic) {
		unsigned rm = (opcode >> 0) & 0xf;
		unsigned rd = (opcode >> 12) & 0xf;

		sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
		return ERROR_OK;
	}

undef:
	/* these opcodes might be used someday */
	sprintf(cp, "UNDEFINED");
	return ERROR_OK;
}

/* Miscellaneous load/store instructions */
static int evaluate_misc_load_store(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t P, U, I, W, L, S, H;
	uint8_t Rn, Rd;
	char *operation; /* "LDR" or "STR" */
	char *suffix; /* "H", "SB", "SH", "D" */
	char offset[32];

	/* examine flags */
	P = (opcode & 0x01000000) >> 24;
	U = (opcode & 0x00800000) >> 23;
	I = (opcode & 0x00400000) >> 22;
	W = (opcode & 0x00200000) >> 21;
	L = (opcode & 0x00100000) >> 20;
	S = (opcode & 0x00000040) >> 6;
	H = (opcode & 0x00000020) >> 5;

	/* target register */
	Rd = (opcode & 0xf000) >> 12;

	/* base register */
	Rn = (opcode & 0xf0000) >> 16;

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = Rn;
	instruction->info.load_store.U = U;

	/* determine instruction type and suffix */
	if (S) /* signed */
	{
		if (L) /* load */
		{
			if (H)
			{
				operation = "LDR";
				instruction->type = ARM_LDRSH;
				suffix = "SH";
			}
			else
			{
				operation = "LDR";
				instruction->type = ARM_LDRSB;
				suffix = "SB";
			}
		}
		else /* there are no signed stores, so this is used to encode double-register load/stores */
		{
			suffix = "D";
			if (H)
			{
				operation = "STR";
				instruction->type = ARM_STRD;
			}
			else
			{
				operation = "LDR";
				instruction->type = ARM_LDRD;
			}
		}
	}
	else /* unsigned */
	{
		suffix = "H";
		if (L) /* load */
		{
			operation = "LDR";
			instruction->type = ARM_LDRH;
		}
		else /* store */
		{
			operation = "STR";
			instruction->type = ARM_STRH;
		}
	}

	if (I) /* Immediate offset/index (#+-<offset_8>)*/
	{
		uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
		snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8);

		instruction->info.load_store.offset_mode = 0;
		instruction->info.load_store.offset.offset = offset_8;
	}
	else /* Register offset/index (+-<Rm>) */
	{
		uint8_t Rm;
		Rm = (opcode & 0xf);
		snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);

		instruction->info.load_store.offset_mode = 1;
		instruction->info.load_store.offset.reg.Rm = Rm;
		instruction->info.load_store.offset.reg.shift = 0x0;
		instruction->info.load_store.offset.reg.shift_imm = 0x0;
	}

	if (P == 1)
	{
		if (W == 0) /* offset */
		{
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]",
					 address, opcode, operation, COND(opcode), suffix,
					 Rd, Rn, offset);

			instruction->info.load_store.index_mode = 0;
		}
		else /* pre-indexed */
		{
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!",
					 address, opcode, operation, COND(opcode), suffix,
					 Rd, Rn, offset);

			instruction->info.load_store.index_mode = 1;
		}
	}
	else /* post-indexed */
	{
		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s",
				 address, opcode, operation, COND(opcode), suffix,
				 Rd, Rn, offset);

		instruction->info.load_store.index_mode = 2;
	}

	return ERROR_OK;
}

/* Load/store multiples instructions */
static int evaluate_ldm_stm(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t P, U, S, W, L, Rn;
	uint32_t register_list;
	char *addressing_mode;
	char *mnemonic;
	char reg_list[69];
	char *reg_list_p;
	int i;
	int first_reg = 1;

	P = (opcode & 0x01000000) >> 24;
	U = (opcode & 0x00800000) >> 23;
	S = (opcode & 0x00400000) >> 22;
	W = (opcode & 0x00200000) >> 21;
	L = (opcode & 0x00100000) >> 20;
	register_list = (opcode & 0xffff);
	Rn = (opcode & 0xf0000) >> 16;

	instruction->info.load_store_multiple.Rn = Rn;
	instruction->info.load_store_multiple.register_list = register_list;
	instruction->info.load_store_multiple.S = S;
	instruction->info.load_store_multiple.W = W;

	if (L)
	{
		instruction->type = ARM_LDM;
		mnemonic = "LDM";
	}
	else
	{
		instruction->type = ARM_STM;
		mnemonic = "STM";
	}

	if (P)
	{
		if (U)
		{
			instruction->info.load_store_multiple.addressing_mode = 1;
			addressing_mode = "IB";
		}
		else
		{
			instruction->info.load_store_multiple.addressing_mode = 3;
			addressing_mode = "DB";
		}
	}
	else
	{
		if (U)
		{
			instruction->info.load_store_multiple.addressing_mode = 0;
			/* "IA" is the default in UAL syntax */
			addressing_mode = "";
		}
		else
		{
			instruction->info.load_store_multiple.addressing_mode = 2;
			addressing_mode = "DA";
		}
	}

	reg_list_p = reg_list;
	for (i = 0; i <= 15; i++)
	{
		if ((register_list >> i) & 1)
		{
			if (first_reg)
			{
				first_reg = 0;
				reg_list_p += snprintf(reg_list_p, (reg_list + 69 - reg_list_p), "r%i", i);
			}
			else
			{
				reg_list_p += snprintf(reg_list_p, (reg_list + 69 - reg_list_p), ", r%i", i);
			}
		}
	}

	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
			 address, opcode, mnemonic, COND(opcode), addressing_mode,
			 Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");

	return ERROR_OK;
}

/* Multiplies, extra load/stores */
static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	/* Multiply (accumulate) (long) and Swap/swap byte */
	if ((opcode & 0x000000f0) == 0x00000090)
	{
		/* Multiply (accumulate) */
		if ((opcode & 0x0f800000) == 0x00000000)
		{
			uint8_t Rm, Rs, Rn, Rd, S;
			Rm = opcode & 0xf;
			Rs = (opcode & 0xf00) >> 8;
			Rn = (opcode & 0xf000) >> 12;
			Rd = (opcode & 0xf0000) >> 16;
			S = (opcode & 0x00100000) >> 20;

			/* examine A bit (accumulate) */
			if (opcode & 0x00200000)
			{
				instruction->type = ARM_MLA;
				snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMLA%s%s r%i, r%i, r%i, r%i",
						address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs, Rn);
			}
			else
			{
				instruction->type = ARM_MUL;
				snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i",
						 address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs);
			}

			return ERROR_OK;
		}

		/* Multiply (accumulate) long */
		if ((opcode & 0x0f800000) == 0x00800000)
		{
			char* mnemonic = NULL;
			uint8_t Rm, Rs, RdHi, RdLow, S;
			Rm = opcode & 0xf;
			Rs = (opcode & 0xf00) >> 8;
			RdHi = (opcode & 0xf000) >> 12;
			RdLow = (opcode & 0xf0000) >> 16;
			S = (opcode & 0x00100000) >> 20;

			switch ((opcode & 0x00600000) >> 21)
			{
				case 0x0:
					instruction->type = ARM_UMULL;
					mnemonic = "UMULL";
					break;
				case 0x1:
					instruction->type = ARM_UMLAL;
					mnemonic = "UMLAL";
					break;
				case 0x2:
					instruction->type = ARM_SMULL;
					mnemonic = "SMULL";
					break;
				case 0x3:
					instruction->type = ARM_SMLAL;
					mnemonic = "SMLAL";
					break;
			}

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i",
						address, opcode, mnemonic, COND(opcode), (S) ? "S" : "",
						RdLow, RdHi, Rm, Rs);

			return ERROR_OK;
		}

		/* Swap/swap byte */
		if ((opcode & 0x0f800000) == 0x01000000)
		{
			uint8_t Rm, Rd, Rn;
			Rm = opcode & 0xf;
			Rd = (opcode & 0xf000) >> 12;
			Rn = (opcode & 0xf0000) >> 16;

			/* examine B flag */
			instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]",
					 address, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), Rd, Rm, Rn);
			return ERROR_OK;
		}

	}

	return evaluate_misc_load_store(opcode, address, instruction);
}

static int evaluate_mrs_msr(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	int R = (opcode & 0x00400000) >> 22;
	char *PSR = (R) ? "SPSR" : "CPSR";

	/* Move register to status register (MSR) */
	if (opcode & 0x00200000)
	{
		instruction->type = ARM_MSR;

		/* immediate variant */
		if (opcode & 0x02000000)
		{
			uint8_t immediate = (opcode & 0xff);
			uint8_t rotate = (opcode & 0xf00);

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32 ,
					 address, opcode, COND(opcode), PSR,
					 (opcode & 0x10000) ? "c" : "",
					 (opcode & 0x20000) ? "x" : "",
					 (opcode & 0x40000) ? "s" : "",
					 (opcode & 0x80000) ? "f" : "",
					 ror(immediate, (rotate * 2))
);
		}
		else /* register variant */
		{
			uint8_t Rm = opcode & 0xf;
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i",
					 address, opcode, COND(opcode), PSR,
					 (opcode & 0x10000) ? "c" : "",
					 (opcode & 0x20000) ? "x" : "",
					 (opcode & 0x40000) ? "s" : "",
					 (opcode & 0x80000) ? "f" : "",
					 Rm
);
		}

	}
	else /* Move status register to register (MRS) */
	{
		uint8_t Rd;

		instruction->type = ARM_MRS;
		Rd = (opcode & 0x0000f000) >> 12;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s",
				 address, opcode, COND(opcode), Rd, PSR);
	}

	return ERROR_OK;
}

/* Miscellaneous instructions */
static int evaluate_misc_instr(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	/* MRS/MSR */
	if ((opcode & 0x000000f0) == 0x00000000)
	{
		evaluate_mrs_msr(opcode, address, instruction);
	}

	/* BX */
	if ((opcode & 0x006000f0) == 0x00200010)
	{
		uint8_t Rm;
		instruction->type = ARM_BX;
		Rm = opcode & 0xf;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i",
				 address, opcode, COND(opcode), Rm);

		instruction->info.b_bl_bx_blx.reg_operand = Rm;
		instruction->info.b_bl_bx_blx.target_address = -1;
	}

	/* BXJ - "Jazelle" support (ARMv5-J) */
	if ((opcode & 0x006000f0) == 0x00200020)
	{
		uint8_t Rm;
		instruction->type = ARM_BX;
		Rm = opcode & 0xf;

		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i",
				 address, opcode, COND(opcode), Rm);

		instruction->info.b_bl_bx_blx.reg_operand = Rm;
		instruction->info.b_bl_bx_blx.target_address = -1;
	}

	/* CLZ */
	if ((opcode & 0x006000f0) == 0x00600010)
	{
		uint8_t Rm, Rd;
		instruction->type = ARM_CLZ;
		Rm = opcode & 0xf;
		Rd = (opcode & 0xf000) >> 12;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i",
				 address, opcode, COND(opcode), Rd, Rm);
	}

	/* BLX(2) */
	if ((opcode & 0x006000f0) == 0x00200030)
	{
		uint8_t Rm;
		instruction->type = ARM_BLX;
		Rm = opcode & 0xf;

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i",
				 address, opcode, COND(opcode), Rm);

		instruction->info.b_bl_bx_blx.reg_operand = Rm;
		instruction->info.b_bl_bx_blx.target_address = -1;
	}

	/* Enhanced DSP add/subtracts */
	if ((opcode & 0x0000000f0) == 0x00000050)
	{
		uint8_t Rm, Rd, Rn;
		char *mnemonic = NULL;
		Rm = opcode & 0xf;
		Rd = (opcode & 0xf000) >> 12;
		Rn = (opcode & 0xf0000) >> 16;

		switch ((opcode & 0x00600000) >> 21)
		{
			case 0x0:
				instruction->type = ARM_QADD;
				mnemonic = "QADD";
				break;
			case 0x1:
				instruction->type = ARM_QSUB;
				mnemonic = "QSUB";
				break;
			case 0x2:
				instruction->type = ARM_QDADD;
				mnemonic = "QDADD";
				break;
			case 0x3:
				instruction->type = ARM_QDSUB;
				mnemonic = "QDSUB";
				break;
		}

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i",
				 address, opcode, mnemonic, COND(opcode), Rd, Rm, Rn);
	}

	/* Software breakpoints */
	if ((opcode & 0x0000000f0) == 0x00000070)
	{
		uint32_t immediate;
		instruction->type = ARM_BKPT;
		immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);

		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
				 address, opcode, immediate);
	}

	/* Enhanced DSP multiplies */
	if ((opcode & 0x000000090) == 0x00000080)
	{
		int x = (opcode & 0x20) >> 5;
		int y = (opcode & 0x40) >> 6;

		/* SMLA < x><y> */
		if ((opcode & 0x00600000) == 0x00000000)
		{
			uint8_t Rd, Rm, Rs, Rn;
			instruction->type = ARM_SMLAxy;
			Rd = (opcode & 0xf0000) >> 16;
			Rm = (opcode & 0xf);
			Rs = (opcode & 0xf00) >> 8;
			Rn = (opcode & 0xf000) >> 12;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
					 Rd, Rm, Rs, Rn);
		}

		/* SMLAL < x><y> */
		if ((opcode & 0x00600000) == 0x00400000)
		{
			uint8_t RdLow, RdHi, Rm, Rs;
			instruction->type = ARM_SMLAxy;
			RdHi = (opcode & 0xf0000) >> 16;
			RdLow = (opcode & 0xf000) >> 12;
			Rm = (opcode & 0xf);
			Rs = (opcode & 0xf00) >> 8;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
					 RdLow, RdHi, Rm, Rs);
		}

		/* SMLAW < y> */
		if (((opcode & 0x00600000) == 0x00100000) && (x == 0))
		{
			uint8_t Rd, Rm, Rs, Rn;
			instruction->type = ARM_SMLAWy;
			Rd = (opcode & 0xf0000) >> 16;
			Rm = (opcode & 0xf);
			Rs = (opcode & 0xf00) >> 8;
			Rn = (opcode & 0xf000) >> 12;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLAW%s%s r%i, r%i, r%i, r%i",
					 address, opcode, (y) ? "T" : "B", COND(opcode),
					 Rd, Rm, Rs, Rn);
		}

		/* SMUL < x><y> */
		if ((opcode & 0x00600000) == 0x00300000)
		{
			uint8_t Rd, Rm, Rs;
			instruction->type = ARM_SMULxy;
			Rd = (opcode & 0xf0000) >> 16;
			Rm = (opcode & 0xf);
			Rs = (opcode & 0xf00) >> 8;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i",
					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
					 Rd, Rm, Rs);
		}

		/* SMULW < y> */
		if (((opcode & 0x00600000) == 0x00100000) && (x == 1))
		{
			uint8_t Rd, Rm, Rs;
			instruction->type = ARM_SMULWy;
			Rd = (opcode & 0xf0000) >> 16;
			Rm = (opcode & 0xf);
			Rs = (opcode & 0xf00) >> 8;

			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i",
					 address, opcode, (y) ? "T" : "B", COND(opcode),
					 Rd, Rm, Rs);
		}
	}

	return ERROR_OK;
}

static int evaluate_data_proc(uint32_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t I, op, S, Rn, Rd;
	char *mnemonic = NULL;
	char shifter_operand[32];

	I = (opcode & 0x02000000) >> 25;
	op = (opcode & 0x01e00000) >> 21;
	S = (opcode & 0x00100000) >> 20;

	Rd = (opcode & 0xf000) >> 12;
	Rn = (opcode & 0xf0000) >> 16;

	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = Rn;
	instruction->info.data_proc.S = S;

	switch (op)
	{
		case 0x0:
			instruction->type = ARM_AND;
			mnemonic = "AND";
			break;
		case 0x1:
			instruction->type = ARM_EOR;
			mnemonic = "EOR";
			break;
		case 0x2:
			instruction->type = ARM_SUB;
			mnemonic = "SUB";
			break;
		case 0x3:
			instruction->type = ARM_RSB;
			mnemonic = "RSB";
			break;
		case 0x4:
			instruction->type = ARM_ADD;
			mnemonic = "ADD";
			break;
		case 0x5:
			instruction->type = ARM_ADC;
			mnemonic = "ADC";
			break;
		case 0x6:
			instruction->type = ARM_SBC;
			mnemonic = "SBC";
			break;
		case 0x7:
			instruction->type = ARM_RSC;
			mnemonic = "RSC";
			break;
		case 0x8:
			instruction->type = ARM_TST;
			mnemonic = "TST";
			break;
		case 0x9:
			instruction->type = ARM_TEQ;
			mnemonic = "TEQ";
			break;
		case 0xa:
			instruction->type = ARM_CMP;
			mnemonic = "CMP";
			break;
		case 0xb:
			instruction->type = ARM_CMN;
			mnemonic = "CMN";
			break;
		case 0xc:
			instruction->type = ARM_ORR;
			mnemonic = "ORR";
			break;
		case 0xd:
			instruction->type = ARM_MOV;
			mnemonic = "MOV";
			break;
		case 0xe:
			instruction->type = ARM_BIC;
			mnemonic = "BIC";
			break;
		case 0xf:
			instruction->type = ARM_MVN;
			mnemonic = "MVN";
			break;
	}

	if (I) /* immediate shifter operand (#<immediate>)*/
	{
		uint8_t immed_8 = opcode & 0xff;
		uint8_t rotate_imm = (opcode & 0xf00) >> 8;
		uint32_t immediate;

		immediate = ror(immed_8, rotate_imm * 2);

		snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);

		instruction->info.data_proc.variant = 0;
		instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
	}
	else /* register-based shifter operand */
	{
		uint8_t shift, Rm;
		shift = (opcode & 0x60) >> 5;
		Rm = (opcode & 0xf);

		if ((opcode & 0x10) != 0x10) /* Immediate shifts ("<Rm>" or "<Rm>, <shift> #<shift_immediate>") */
		{
			uint8_t shift_imm;
			shift_imm = (opcode & 0xf80) >> 7;

			instruction->info.data_proc.variant = 1;
			instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
			instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
			instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;

			/* LSR encodes a shift by 32 bit as 0x0 */
			if ((shift == 0x1) && (shift_imm == 0x0))
				shift_imm = 0x20;

			/* ASR encodes a shift by 32 bit as 0x0 */
			if ((shift == 0x2) && (shift_imm == 0x0))
				shift_imm = 0x20;

			/* ROR by 32 bit is actually a RRX */
			if ((shift == 0x3) && (shift_imm == 0x0))
				shift = 0x4;

			if ((shift_imm == 0x0) && (shift == 0x0))
			{
				snprintf(shifter_operand, 32, "r%i", Rm);
			}
			else
			{
				if (shift == 0x0) /* LSL */
				{
					snprintf(shifter_operand, 32, "r%i, LSL #0x%x", Rm, shift_imm);
				}
				else if (shift == 0x1) /* LSR */
				{
					snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm);
				}
				else if (shift == 0x2) /* ASR */
				{
					snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm);
				}
				else if (shift == 0x3) /* ROR */
				{
					snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
				}
				else if (shift == 0x4) /* RRX */
				{
					snprintf(shifter_operand, 32, "r%i, RRX", Rm);
				}
			}
		}
		else /* Register shifts ("<Rm>, <shift> <Rs>") */
		{
			uint8_t Rs = (opcode & 0xf00) >> 8;

			instruction->info.data_proc.variant = 2;
			instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
			instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs;
			instruction->info.data_proc.shifter_operand.register_shift.shift = shift;

			if (shift == 0x0) /* LSL */
			{
				snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs);
			}
			else if (shift == 0x1) /* LSR */
			{
				snprintf(shifter_operand, 32, "r%i, LSR r%i", Rm, Rs);
			}
			else if (shift == 0x2) /* ASR */
			{
				snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
			}
			else if (shift == 0x3) /* ROR */
			{
				snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
			}
		}
	}

	if ((op < 0x8) || (op == 0xc) || (op == 0xe)) /* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> */
	{
		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s",
				 address, opcode, mnemonic, COND(opcode),
				 (S) ? "S" : "", Rd, Rn, shifter_operand);
	}
	else if ((op == 0xd) || (op == 0xf)) /* <opcode1>{<cond>}{S} <Rd>, <shifter_operand> */
	{
		if (opcode == 0xe1a00000) /* print MOV r0,r0 as NOP */
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tNOP",address, opcode);
		else
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, %s",
				 address, opcode, mnemonic, COND(opcode),
				 (S) ? "S" : "", Rd, shifter_operand);
	}
	else /* <opcode2>{<cond>} <Rn>, <shifter_operand> */
	{
		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s",
				 address, opcode, mnemonic, COND(opcode),
				 Rn, shifter_operand);
	}

	return ERROR_OK;
}

int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
{
	/* clear fields, to avoid confusion */
	memset(instruction, 0, sizeof(arm_instruction_t));
	instruction->opcode = opcode;
	instruction->instruction_size = 4;

	/* catch opcodes with condition field [31:28] = b1111 */
	if ((opcode & 0xf0000000) == 0xf0000000)
	{
		/* Undefined instruction (or ARMv5E cache preload PLD) */
		if ((opcode & 0x08000000) == 0x00000000)
			return evaluate_pld(opcode, address, instruction);

		/* Undefined instruction */
		if ((opcode & 0x0e000000) == 0x08000000)
		{
			instruction->type = ARM_UNDEFINED_INSTRUCTION;
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
			return ERROR_OK;
		}

		/* Branch and branch with link and change to Thumb */
		if ((opcode & 0x0e000000) == 0x0a000000)
			return evaluate_blx_imm(opcode, address, instruction);

		/* Extended coprocessor opcode space (ARMv5 and higher)*/
		/* Coprocessor load/store and double register transfers */
		if ((opcode & 0x0e000000) == 0x0c000000)
			return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);

		/* Coprocessor data processing */
		if ((opcode & 0x0f000100) == 0x0c000000)
			return evaluate_cdp_mcr_mrc(opcode, address, instruction);

		/* Coprocessor register transfers */
		if ((opcode & 0x0f000010) == 0x0c000010)
			return evaluate_cdp_mcr_mrc(opcode, address, instruction);

		/* Undefined instruction */
		if ((opcode & 0x0f000000) == 0x0f000000)
		{
			instruction->type = ARM_UNDEFINED_INSTRUCTION;
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
			return ERROR_OK;
		}
	}

	/* catch opcodes with [27:25] = b000 */
	if ((opcode & 0x0e000000) == 0x00000000)
	{
		/* Multiplies, extra load/stores */
		if ((opcode & 0x00000090) == 0x00000090)
			return evaluate_mul_and_extra_ld_st(opcode, address, instruction);

		/* Miscellaneous instructions */
		if ((opcode & 0x0f900000) == 0x01000000)
			return evaluate_misc_instr(opcode, address, instruction);

		return evaluate_data_proc(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b001 */
	if ((opcode & 0x0e000000) == 0x02000000)
	{
		/* Undefined instruction */
		if ((opcode & 0x0fb00000) == 0x03000000)
		{
			instruction->type = ARM_UNDEFINED_INSTRUCTION;
			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
			return ERROR_OK;
		}

		/* Move immediate to status register */
		if ((opcode & 0x0fb00000) == 0x03200000)
			return evaluate_mrs_msr(opcode, address, instruction);

		return evaluate_data_proc(opcode, address, instruction);

	}

	/* catch opcodes with [27:25] = b010 */
	if ((opcode & 0x0e000000) == 0x04000000)
	{
		/* Load/store immediate offset */
		return evaluate_load_store(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b011 */
	if ((opcode & 0x0e000000) == 0x06000000)
	{
		/* Load/store register offset */
		if ((opcode & 0x00000010) == 0x00000000)
			return evaluate_load_store(opcode, address, instruction);

		/* Architecturally Undefined instruction
		 * ... don't expect these to ever be used
		 */
		if ((opcode & 0x07f000f0) == 0x07f000f0)
		{
			instruction->type = ARM_UNDEFINED_INSTRUCTION;
			snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEF",
				address, opcode);
			return ERROR_OK;
		}

		/* "media" instructions */
		return evaluate_media(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b100 */
	if ((opcode & 0x0e000000) == 0x08000000)
	{
		/* Load/store multiple */
		return evaluate_ldm_stm(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b101 */
	if ((opcode & 0x0e000000) == 0x0a000000)
	{
		/* Branch and branch with link */
		return evaluate_b_bl(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b110 */
	if ((opcode & 0x0e000000) == 0x0a000000)
	{
		/* Coprocessor load/store and double register transfers */
		return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);
	}

	/* catch opcodes with [27:25] = b111 */
	if ((opcode & 0x0e000000) == 0x0e000000)
	{
		/* Software interrupt */
		if ((opcode & 0x0f000000) == 0x0f000000)
			return evaluate_swi(opcode, address, instruction);

		/* Coprocessor data processing */
		if ((opcode & 0x0f000010) == 0x0e000000)
			return evaluate_cdp_mcr_mrc(opcode, address, instruction);

		/* Coprocessor register transfers */
		if ((opcode & 0x0f000010) == 0x0e000010)
			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
	}

	LOG_ERROR("should never reach this point");
	return -1;
}

static int evaluate_b_bl_blx_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t offset = opcode & 0x7ff;
	uint32_t opc = (opcode >> 11) & 0x3;
	uint32_t target_address;
	char *mnemonic = NULL;

	/* sign extend 11-bit offset */
	if (((opc == 0) || (opc == 2)) && (offset & 0x00000400))
		offset = 0xfffff800 | offset;

	target_address = address + 4 + (offset << 1);

	switch (opc)
	{
		/* unconditional branch */
		case 0:
			instruction->type = ARM_B;
			mnemonic = "B";
			break;
		/* BLX suffix */
		case 1:
			instruction->type = ARM_BLX;
			mnemonic = "BLX";
			target_address &= 0xfffffffc;
			break;
		/* BL/BLX prefix */
		case 2:
			instruction->type = ARM_UNKNOWN_INSTUCTION;
			mnemonic = "prefix";
			target_address = offset << 12;
			break;
		/* BL suffix */
		case 3:
			instruction->type = ARM_BL;
			mnemonic = "BL";
			break;
	}

	/* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
	 * these are effectively 32-bit instructions even in Thumb1.
	 * Might be simplest to always use the Thumb2 decoder.
	 */

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\t%#8.8" PRIx32,
			address, opcode, mnemonic, target_address);

	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = target_address;

	return ERROR_OK;
}

static int evaluate_add_sub_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t Rd = (opcode >> 0) & 0x7;
	uint8_t Rn = (opcode >> 3) & 0x7;
	uint8_t Rm_imm = (opcode >> 6) & 0x7;
	uint32_t opc = opcode & (1 << 9);
	uint32_t reg_imm  = opcode & (1 << 10);
	char *mnemonic;

	if (opc)
	{
		instruction->type = ARM_SUB;
		mnemonic = "SUBS";
	}
	else
	{
		/* REVISIT:  if reg_imm == 0, display as "MOVS" */
		instruction->type = ARM_ADD;
		mnemonic = "ADDS";
	}

	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = Rn;
	instruction->info.data_proc.S = 1;

	if (reg_imm)
	{
		instruction->info.data_proc.variant = 0; /*immediate*/
		instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
		snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%d",
			address, opcode, mnemonic, Rd, Rn, Rm_imm);
	}
	else
	{
		instruction->info.data_proc.variant = 1; /*immediate shift*/
		instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
		snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, r%i",
			address, opcode, mnemonic, Rd, Rn, Rm_imm);
	}

	return ERROR_OK;
}

static int evaluate_shift_imm_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t Rd = (opcode >> 0) & 0x7;
	uint8_t Rm = (opcode >> 3) & 0x7;
	uint8_t imm = (opcode >> 6) & 0x1f;
	uint8_t opc = (opcode >> 11) & 0x3;
	char *mnemonic = NULL;

	switch (opc)
	{
		case 0:
			instruction->type = ARM_MOV;
			mnemonic = "LSLS";
			instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0;
			break;
		case 1:
			instruction->type = ARM_MOV;
			mnemonic = "LSRS";
			instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1;
			break;
		case 2:
			instruction->type = ARM_MOV;
			mnemonic = "ASRS";
			instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2;
			break;
	}

	if ((imm == 0) && (opc != 0))
		imm = 32;

	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = -1;
	instruction->info.data_proc.S = 1;

	instruction->info.data_proc.variant = 1; /*immediate_shift*/
	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
	instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%#2.2x" ,
			address, opcode, mnemonic, Rd, Rm, imm);

	return ERROR_OK;
}

static int evaluate_data_proc_imm_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t imm = opcode & 0xff;
	uint8_t Rd = (opcode >> 8) & 0x7;
	uint32_t opc = (opcode >> 11) & 0x3;
	char *mnemonic = NULL;

	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = Rd;
	instruction->info.data_proc.S = 1;
	instruction->info.data_proc.variant = 0; /*immediate*/
	instruction->info.data_proc.shifter_operand.immediate.immediate = imm;

	switch (opc)
	{
		case 0:
			instruction->type = ARM_MOV;
			mnemonic = "MOVS";
			instruction->info.data_proc.Rn = -1;
			break;
		case 1:
			instruction->type = ARM_CMP;
			mnemonic = "CMP";
			instruction->info.data_proc.Rd = -1;
			break;
		case 2:
			instruction->type = ARM_ADD;
			mnemonic = "ADDS";
			break;
		case 3:
			instruction->type = ARM_SUB;
			mnemonic = "SUBS";
			break;
	}

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, #%#2.2x",
			address, opcode, mnemonic, Rd, imm);

	return ERROR_OK;
}

static int evaluate_data_proc_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t high_reg, op, Rm, Rd,H1,H2;
	char *mnemonic = NULL;
	bool nop = false;

	high_reg = (opcode & 0x0400) >> 10;
	op = (opcode & 0x03C0) >> 6;

	Rd = (opcode & 0x0007);
	Rm = (opcode & 0x0038) >> 3;
	H1 = (opcode & 0x0080) >> 7;
	H2 = (opcode & 0x0040) >> 6;

	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = Rd;
	instruction->info.data_proc.S = (!high_reg || (instruction->type == ARM_CMP));
	instruction->info.data_proc.variant = 1 /*immediate shift*/;
	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;

	if (high_reg)
	{
		Rd |= H1 << 3;
		Rm |= H2 << 3;
		op >>= 2;

		switch (op)
		{
			case 0x0:
				instruction->type = ARM_ADD;
				mnemonic = "ADD";
				break;
			case 0x1:
				instruction->type = ARM_CMP;
				mnemonic = "CMP";
				break;
			case 0x2:
				instruction->type = ARM_MOV;
				mnemonic = "MOV";
				if (Rd == Rm)
					nop = true;
				break;
			case 0x3:
				if ((opcode & 0x7) == 0x0)
				{
					instruction->info.b_bl_bx_blx.reg_operand = Rm;
					if (H1)
					{
						instruction->type = ARM_BLX;
						snprintf(instruction->text, 128,
							"0x%8.8" PRIx32
							"  0x%4.4x    \tBLX\tr%i",
							address, opcode, Rm);
					}
					else
					{
						instruction->type = ARM_BX;
						snprintf(instruction->text, 128,
							"0x%8.8" PRIx32
							"  0x%4.4x    \tBX\tr%i",
							address, opcode, Rm);
					}
				}
				else
				{
					instruction->type = ARM_UNDEFINED_INSTRUCTION;
					snprintf(instruction->text, 128,
						"0x%8.8" PRIx32
						"  0x%4.4x    \t"
						"UNDEFINED INSTRUCTION",
						address, opcode);
				}
				return ERROR_OK;
				break;
		}
	}
	else
	{
		switch (op)
		{
			case 0x0:
				instruction->type = ARM_AND;
				mnemonic = "ANDS";
				break;
			case 0x1:
				instruction->type = ARM_EOR;
				mnemonic = "EORS";
				break;
			case 0x2:
				instruction->type = ARM_MOV;
				mnemonic = "LSLS";
				instruction->info.data_proc.variant = 2 /*register shift*/;
				instruction->info.data_proc.shifter_operand.register_shift.shift = 0;
				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
				break;
			case 0x3:
				instruction->type = ARM_MOV;
				mnemonic = "LSRS";
				instruction->info.data_proc.variant = 2 /*register shift*/;
				instruction->info.data_proc.shifter_operand.register_shift.shift = 1;
				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
				break;
			case 0x4:
				instruction->type = ARM_MOV;
				mnemonic = "ASRS";
				instruction->info.data_proc.variant = 2 /*register shift*/;
				instruction->info.data_proc.shifter_operand.register_shift.shift = 2;
				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
				break;
			case 0x5:
				instruction->type = ARM_ADC;
				mnemonic = "ADCS";
				break;
			case 0x6:
				instruction->type = ARM_SBC;
				mnemonic = "SBCS";
				break;
			case 0x7:
				instruction->type = ARM_MOV;
				mnemonic = "RORS";
				instruction->info.data_proc.variant = 2 /*register shift*/;
				instruction->info.data_proc.shifter_operand.register_shift.shift = 3;
				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
				break;
			case 0x8:
				instruction->type = ARM_TST;
				mnemonic = "TST";
				break;
			case 0x9:
				instruction->type = ARM_RSB;
				mnemonic = "RSBS";
				instruction->info.data_proc.variant = 0 /*immediate*/;
				instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
				instruction->info.data_proc.Rn = Rm;
				break;
			case 0xA:
				instruction->type = ARM_CMP;
				mnemonic = "CMP";
				break;
			case 0xB:
				instruction->type = ARM_CMN;
				mnemonic = "CMN";
				break;
			case 0xC:
				instruction->type = ARM_ORR;
				mnemonic = "ORRS";
				break;
			case 0xD:
				instruction->type = ARM_MUL;
				mnemonic = "MULS";
				break;
			case 0xE:
				instruction->type = ARM_BIC;
				mnemonic = "BICS";
				break;
			case 0xF:
				instruction->type = ARM_MVN;
				mnemonic = "MVNS";
				break;
		}
	}

	if (nop)
		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "  0x%4.4x    \tNOP\t\t\t"
				"; (%s r%i, r%i)",
				 address, opcode, mnemonic, Rd, Rm);
	else
		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i",
				 address, opcode, mnemonic, Rd, Rm);

	return ERROR_OK;
}

/* PC-relative data addressing is word-aligned even with Thumb */
static inline uint32_t thumb_alignpc4(uint32_t addr)
{
	return (addr + 4) & ~3;
}

static int evaluate_load_literal_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t immediate;
	uint8_t Rd = (opcode >> 8) & 0x7;

	instruction->type = ARM_LDR;
	immediate = opcode & 0x000000ff;
	immediate *= 4;

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = 15 /*PC*/;
	instruction->info.load_store.index_mode = 0; /*offset*/
	instruction->info.load_store.offset_mode = 0; /*immediate*/
	instruction->info.load_store.offset.offset = immediate;

	snprintf(instruction->text, 128,
		"0x%8.8" PRIx32 "  0x%4.4x    \t"
		"LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32,
		address, opcode, Rd, immediate,
		thumb_alignpc4(address) + immediate);

	return ERROR_OK;
}

static int evaluate_load_store_reg_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint8_t Rd = (opcode >> 0) & 0x7;
	uint8_t Rn = (opcode >> 3) & 0x7;
	uint8_t Rm = (opcode >> 6) & 0x7;
	uint8_t opc = (opcode >> 9) & 0x7;
	char *mnemonic = NULL;

	switch (opc)
	{
		case 0:
			instruction->type = ARM_STR;
			mnemonic = "STR";
			break;
		case 1:
			instruction->type = ARM_STRH;
			mnemonic = "STRH";
			break;
		case 2:
			instruction->type = ARM_STRB;
			mnemonic = "STRB";
			break;
		case 3:
			instruction->type = ARM_LDRSB;
			mnemonic = "LDRSB";
			break;
		case 4:
			instruction->type = ARM_LDR;
			mnemonic = "LDR";
			break;
		case 5:
			instruction->type = ARM_LDRH;
			mnemonic = "LDRH";
			break;
		case 6:
			instruction->type = ARM_LDRB;
			mnemonic = "LDRB";
			break;
		case 7:
			instruction->type = ARM_LDRSH;
			mnemonic = "LDRSH";
			break;
	}

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [r%i, r%i]",
			address, opcode, mnemonic, Rd, Rn, Rm);

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = Rn;
	instruction->info.load_store.index_mode = 0; /*offset*/
	instruction->info.load_store.offset_mode = 1; /*register*/
	instruction->info.load_store.offset.reg.Rm = Rm;

	return ERROR_OK;
}

static int evaluate_load_store_imm_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t offset = (opcode >> 6) & 0x1f;
	uint8_t Rd = (opcode >> 0) & 0x7;
	uint8_t Rn = (opcode >> 3) & 0x7;
	uint32_t L = opcode & (1 << 11);
	uint32_t B = opcode & (1 << 12);
	char *mnemonic;
	char suffix = ' ';
	uint32_t shift = 2;

	if (L)
	{
		instruction->type = ARM_LDR;
		mnemonic = "LDR";
	}
	else
	{
		instruction->type = ARM_STR;
		mnemonic = "STR";
	}

	if ((opcode&0xF000) == 0x8000)
	{
		suffix = 'H';
		shift = 1;
	}
	else if (B)
	{
		suffix = 'B';
		shift = 0;
	}

	snprintf(instruction->text, 128,
		"0x%8.8" PRIx32 "  0x%4.4x    \t%s%c\tr%i, [r%i, #%#" PRIx32 "]",
		address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = Rn;
	instruction->info.load_store.index_mode = 0; /*offset*/
	instruction->info.load_store.offset_mode = 0; /*immediate*/
	instruction->info.load_store.offset.offset = offset << shift;

	return ERROR_OK;
}

static int evaluate_load_store_stack_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t offset = opcode  & 0xff;
	uint8_t Rd = (opcode >> 8) & 0x7;
	uint32_t L = opcode & (1 << 11);
	char *mnemonic;

	if (L)
	{
		instruction->type = ARM_LDR;
		mnemonic = "LDR";
	}
	else
	{
		instruction->type = ARM_STR;
		mnemonic = "STR";
	}

	snprintf(instruction->text, 128,
		"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [SP, #%#" PRIx32 "]",
		address, opcode, mnemonic, Rd, offset*4);

	instruction->info.load_store.Rd = Rd;
	instruction->info.load_store.Rn = 13 /*SP*/;
	instruction->info.load_store.index_mode = 0; /*offset*/
	instruction->info.load_store.offset_mode = 0; /*immediate*/
	instruction->info.load_store.offset.offset = offset*4;

	return ERROR_OK;
}

static int evaluate_add_sp_pc_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t imm = opcode  & 0xff;
	uint8_t Rd = (opcode >> 8) & 0x7;
	uint8_t Rn;
	uint32_t SP = opcode & (1 << 11);
	char *reg_name;

	instruction->type = ARM_ADD;

	if (SP)
	{
		reg_name = "SP";
		Rn = 13;
	}
	else
	{
		reg_name = "PC";
		Rn = 15;
	}

	snprintf(instruction->text, 128,
		"0x%8.8" PRIx32 "  0x%4.4x  \tADD\tr%i, %s, #%#" PRIx32,
		address, opcode, Rd, reg_name, imm * 4);

	instruction->info.data_proc.variant = 0 /* immediate */;
	instruction->info.data_proc.Rd = Rd;
	instruction->info.data_proc.Rn = Rn;
	instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;

	return ERROR_OK;
}

static int evaluate_adjust_stack_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t imm = opcode  & 0x7f;
	uint8_t opc = opcode & (1 << 7);
	char *mnemonic;


	if (opc)
	{
		instruction->type = ARM_SUB;
		mnemonic = "SUB";
	}
	else
	{
		instruction->type = ARM_ADD;
		mnemonic = "ADD";
	}

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tSP, #%#" PRIx32,
			address, opcode, mnemonic, imm*4);

	instruction->info.data_proc.variant = 0 /* immediate */;
	instruction->info.data_proc.Rd = 13 /*SP*/;
	instruction->info.data_proc.Rn = 13 /*SP*/;
	instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;

	return ERROR_OK;
}

static int evaluate_breakpoint_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t imm = opcode  & 0xff;

	instruction->type = ARM_BKPT;

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x  \tBKPT\t%#2.2" PRIx32 "",
			address, opcode, imm);

	return ERROR_OK;
}

static int evaluate_load_store_multiple_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t reg_list = opcode  & 0xff;
	uint32_t L = opcode & (1 << 11);
	uint32_t R = opcode & (1 << 8);
	uint8_t Rn = (opcode >> 8) & 7;
	uint8_t addr_mode = 0 /* IA */;
	char reg_names[40];
	char *reg_names_p;
	char *mnemonic;
	char ptr_name[7] = "";
	int i;

	/* REVISIT:  in ThumbEE mode, there are no LDM or STM instructions.
	 * The STMIA and LDMIA opcodes are used for other instructions.
	 */

	if ((opcode & 0xf000) == 0xc000)
	{ /* generic load/store multiple */
		char *wback = "!";

		if (L)
		{
			instruction->type = ARM_LDM;
			mnemonic = "LDM";
			if (opcode & (1 << Rn))
				wback = "";
		}
		else
		{
			instruction->type = ARM_STM;
			mnemonic = "STM";
		}
		snprintf(ptr_name, sizeof ptr_name, "r%i%s, ", Rn, wback);
	}
	else
	{ /* push/pop */
		Rn = 13; /* SP */
		if (L)
		{
			instruction->type = ARM_LDM;
			mnemonic = "POP";
			if (R)
				reg_list |= (1 << 15) /*PC*/;
		}
		else
		{
			instruction->type = ARM_STM;
			mnemonic = "PUSH";
			addr_mode = 3; /*DB*/
			if (R)
				reg_list |= (1 << 14) /*LR*/;
		}
	}

	reg_names_p = reg_names;
	for (i = 0; i <= 15; i++)
	{
		if (reg_list & (1 << i))
			reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i);
	}
	if (reg_names_p > reg_names)
		reg_names_p[-2] = '\0';
	else /* invalid op : no registers */
		reg_names[0] = '\0';

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x  \t%s\t%s{%s}",
			address, opcode, mnemonic, ptr_name, reg_names);

	instruction->info.load_store_multiple.register_list = reg_list;
	instruction->info.load_store_multiple.Rn = Rn;
	instruction->info.load_store_multiple.addressing_mode = addr_mode;

	return ERROR_OK;
}

static int evaluate_cond_branch_thumb(uint16_t opcode,
		uint32_t address, arm_instruction_t *instruction)
{
	uint32_t offset = opcode  & 0xff;
	uint8_t cond = (opcode >> 8) & 0xf;
	uint32_t target_address;

	if (cond == 0xf)
	{
		instruction->type = ARM_SWI;
		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "  0x%4.4x    \tSVC\t%#2.2" PRIx32,
				address, opcode, offset);
		return ERROR_OK;
	}
	else if (cond == 0xe)
	{
		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tUNDEFINED INSTRUCTION",
			address, opcode);
		return ERROR_OK;
	}

	/* sign extend 8-bit offset */
	if (offset & 0x00000080)
		offset = 0xffffff00 | offset;

	target_address = address + 4 + (offset << 1);

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tB%s\t%#8.8" PRIx32,
			address, opcode,
			arm_condition_strings[cond], target_address);

	instruction->type = ARM_B;
	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = target_address;

	return ERROR_OK;
}

static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	unsigned offset;

	/* added in Thumb2 */
	offset = (opcode >> 3) & 0x1f;
	offset |= (opcode & 0x0200) >> 4;

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tCB%sZ\tr%d, %#8.8" PRIx32,
			address, opcode,
			(opcode & 0x0800) ? "N" : "",
			opcode & 0x7, address + 4 + (offset << 1));

	return ERROR_OK;
}

static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	/* added in ARMv6 */
	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%cXT%c\tr%d, r%d",
			address, opcode,
			(opcode & 0x0080) ? 'U' : 'S',
			(opcode & 0x0040) ? 'B' : 'H',
			opcode & 0x7, (opcode >> 3) & 0x7);

	return ERROR_OK;
}

static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	/* added in ARMv6 */
	if ((opcode & 0x0ff0) == 0x0650)
		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "  0x%4.4x    \tSETEND %s",
				address, opcode,
				(opcode & 0x80) ? "BE" : "LE");
	else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
		snprintf(instruction->text, 128,
				"0x%8.8" PRIx32 "  0x%4.4x    \tCPSI%c\t%s%s%s",
				address, opcode,
				(opcode & 0x0010) ? 'D' : 'E',
				(opcode & 0x0004) ? "A" : "",
				(opcode & 0x0002) ? "I" : "",
				(opcode & 0x0001) ? "F" : "");

	return ERROR_OK;
}

static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	char *suffix;

	/* added in ARMv6 */
	switch ((opcode >> 6) & 3) {
	case 0:
		suffix = "";
		break;
	case 1:
		suffix = "16";
		break;
	default:
		suffix = "SH";
		break;
	}
	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tREV%s\tr%d, r%d",
			address, opcode, suffix,
			opcode & 0x7, (opcode >> 3) & 0x7);

	return ERROR_OK;
}

static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	char *hint;

	switch ((opcode >> 4) & 0x0f) {
	case 0:
		hint = "NOP";
		break;
	case 1:
		hint = "YIELD";
		break;
	case 2:
		hint = "WFE";
		break;
	case 3:
		hint = "WFI";
		break;
	case 4:
		hint = "SEV";
		break;
	default:
		hint = "HINT (UNRECOGNIZED)";
		break;
	}

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \t%s",
			address, opcode, hint);

	return ERROR_OK;
}

static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
		arm_instruction_t *instruction)
{
	unsigned cond = (opcode >> 4) & 0x0f;
	char *x = "", *y = "", *z = "";

	if (opcode & 0x01)
		z = (opcode & 0x02) ? "T" : "E";
	if (opcode & 0x03)
		y = (opcode & 0x04) ? "T" : "E";
	if (opcode & 0x07)
		x = (opcode & 0x08) ? "T" : "E";

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tIT%s%s%s\t%s",
			address, opcode,
			x, y, z, arm_condition_strings[cond]);

	/* NOTE:  strictly speaking, the next 1-4 instructions should
	 * now be displayed with the relevant conditional suffix...
	 */

	return ERROR_OK;
}

int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
{
	/* clear fields, to avoid confusion */
	memset(instruction, 0, sizeof(arm_instruction_t));
	instruction->opcode = opcode;
	instruction->instruction_size = 2;

	if ((opcode & 0xe000) == 0x0000)
	{
		/* add/substract register or immediate */
		if ((opcode & 0x1800) == 0x1800)
			return evaluate_add_sub_thumb(opcode, address, instruction);
		/* shift by immediate */
		else
			return evaluate_shift_imm_thumb(opcode, address, instruction);
	}

	/* Add/substract/compare/move immediate */
	if ((opcode & 0xe000) == 0x2000)
	{
		return evaluate_data_proc_imm_thumb(opcode, address, instruction);
	}

	/* Data processing instructions */
	if ((opcode & 0xf800) == 0x4000)
	{
		return evaluate_data_proc_thumb(opcode, address, instruction);
	}

	/* Load from literal pool */
	if ((opcode & 0xf800) == 0x4800)
	{
		return evaluate_load_literal_thumb(opcode, address, instruction);
	}

	/* Load/Store register offset */
	if ((opcode & 0xf000) == 0x5000)
	{
		return evaluate_load_store_reg_thumb(opcode, address, instruction);
	}

	/* Load/Store immediate offset */
	if (((opcode & 0xe000) == 0x6000)
		||((opcode & 0xf000) == 0x8000))
	{
		return evaluate_load_store_imm_thumb(opcode, address, instruction);
	}

	/* Load/Store from/to stack */
	if ((opcode & 0xf000) == 0x9000)
	{
		return evaluate_load_store_stack_thumb(opcode, address, instruction);
	}

	/* Add to SP/PC */
	if ((opcode & 0xf000) == 0xa000)
	{
		return evaluate_add_sp_pc_thumb(opcode, address, instruction);
	}

	/* Misc */
	if ((opcode & 0xf000) == 0xb000)
	{
		switch ((opcode >> 8) & 0x0f) {
		case 0x0:
			return evaluate_adjust_stack_thumb(opcode, address, instruction);
		case 0x1:
		case 0x3:
		case 0x9:
		case 0xb:
			return evaluate_cb_thumb(opcode, address, instruction);
		case 0x2:
			return evaluate_extend_thumb(opcode, address, instruction);
		case 0x4:
		case 0x5:
		case 0xc:
		case 0xd:
			return evaluate_load_store_multiple_thumb(opcode, address,
						instruction);
		case 0x6:
			return evaluate_cps_thumb(opcode, address, instruction);
		case 0xa:
			if ((opcode & 0x00c0) == 0x0080)
				break;
			return evaluate_byterev_thumb(opcode, address, instruction);
		case 0xe:
			return evaluate_breakpoint_thumb(opcode, address, instruction);
		case 0xf:
			if (opcode & 0x000f)
				return evaluate_ifthen_thumb(opcode, address,
						instruction);
			else
				return evaluate_hint_thumb(opcode, address,
						instruction);
		}

		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%4.4x    \tUNDEFINED INSTRUCTION",
			address, opcode);
		return ERROR_OK;
	}

	/* Load/Store multiple */
	if ((opcode & 0xf000) == 0xc000)
	{
		return evaluate_load_store_multiple_thumb(opcode, address, instruction);
	}

	/* Conditional branch + SWI */
	if ((opcode & 0xf000) == 0xd000)
	{
		return evaluate_cond_branch_thumb(opcode, address, instruction);
	}

	if ((opcode & 0xe000) == 0xe000)
	{
		/* Undefined instructions */
		if ((opcode & 0xf801) == 0xe801)
		{
			instruction->type = ARM_UNDEFINED_INSTRUCTION;
			snprintf(instruction->text, 128,
					"0x%8.8" PRIx32 "  0x%8.8x\t"
					"UNDEFINED INSTRUCTION",
					address, opcode);
			return ERROR_OK;
		}
		else
		{ /* Branch to offset */
			return evaluate_b_bl_blx_thumb(opcode, address, instruction);
		}
	}

	LOG_ERROR("should never reach this point (opcode=%04x)",opcode);
	return -1;
}

static int t2ev_b_bl(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	unsigned offset;
	unsigned b21 = 1 << 21;
	unsigned b22 = 1 << 22;

	/* instead of combining two smaller 16-bit branch instructions,
	 * Thumb2 uses only one larger 32-bit instruction.
	 */
	offset = opcode & 0x7ff;
	offset |= (opcode & 0x03ff0000) >> 5;
	if (opcode & (1 << 26)) {
		offset |= 0xff << 23;
		if ((opcode & (1 << 11)) == 0)
			b21 = 0;
		if ((opcode & (1 << 13)) == 0)
			b22 = 0;
	} else {
		if (opcode & (1 << 11))
			b21 = 0;
		if (opcode & (1 << 13))
			b22 = 0;
	}
	offset |= b21;
	offset |= b22;


	address += 4;
	address += offset << 1;

	instruction->type = (opcode & (1 << 14)) ? ARM_BL : ARM_B;
	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = address;
	sprintf(cp, "%s\t%#8.8" PRIx32,
			(opcode & (1 << 14)) ? "BL" : "B.W",
			address);

	return ERROR_OK;
}

static int t2ev_cond_b(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	unsigned offset;
	unsigned b17 = 1 << 17;
	unsigned b18 = 1 << 18;
	unsigned cond = (opcode >> 22) & 0x0f;

	offset = opcode & 0x7ff;
	offset |= (opcode & 0x003f0000) >> 5;
	if (opcode & (1 << 26)) {
		offset |= 0xffff << 19;
		if ((opcode & (1 << 11)) == 0)
			b17 = 0;
		if ((opcode & (1 << 13)) == 0)
			b18 = 0;
	} else {
		if (opcode & (1 << 11))
			b17 = 0;
		if (opcode & (1 << 13))
			b18 = 0;
	}
	offset |= b17;
	offset |= b18;

	address += 4;
	address += offset << 1;

	instruction->type = ARM_B;
	instruction->info.b_bl_bx_blx.reg_operand = -1;
	instruction->info.b_bl_bx_blx.target_address = address;
	sprintf(cp, "B%s.W\t%#8.8" PRIx32,
			arm_condition_strings[cond],
			address);

	return ERROR_OK;
}

static const char *special_name(int number)
{
	char *special = "(RESERVED)";

	switch (number) {
	case 0:
		special = "apsr";
		break;
	case 1:
		special = "iapsr";
		break;
	case 2:
		special = "eapsr";
		break;
	case 3:
		special = "xpsr";
		break;
	case 5:
		special = "ipsr";
		break;
	case 6:
		special = "epsr";
		break;
	case 7:
		special = "iepsr";
		break;
	case 8:
		special = "msp";
		break;
	case 9:
		special = "psp";
		break;
	case 16:
		special = "primask";
		break;
	case 17:
		special = "basepri";
		break;
	case 18:
		special = "basepri_max";
		break;
	case 19:
		special = "faultmask";
		break;
	case 20:
		special = "control";
		break;
	}
	return special;
}

static int t2ev_hint(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	const char *mnemonic;

	if (opcode & 0x0700) {
		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		strcpy(cp, "UNDEFINED");
		return ERROR_OK;
	}

	if (opcode & 0x00f0) {
		sprintf(cp, "DBG\t#%d", (int) opcode & 0xf);
		return ERROR_OK;
	}

	switch (opcode & 0x0f) {
	case 0:
		mnemonic = "NOP.W";
		break;
	case 1:
		mnemonic = "YIELD.W";
		break;
	case 2:
		mnemonic = "WFE.W";
		break;
	case 3:
		mnemonic = "WFI.W";
		break;
	case 4:
		mnemonic = "SEV.W";
		break;
	default:
		mnemonic = "HINT.W (UNRECOGNIZED)";
		break;
	}
	strcpy(cp, mnemonic);
	return ERROR_OK;
}

static int t2ev_misc(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	const char *mnemonic;

	switch ((opcode >> 4) & 0x0f) {
	case 0:
		mnemonic = "LEAVEX";
		break;
	case 1:
		mnemonic = "ENTERX";
		break;
	case 2:
		mnemonic = "CLREX";
		break;
	case 4:
		mnemonic = "DSB";
		break;
	case 5:
		mnemonic = "DMB";
		break;
	case 6:
		mnemonic = "ISB";
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}
	strcpy(cp, mnemonic);
	return ERROR_OK;
}

static int t2ev_b_misc(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	/* permanently undefined */
	if ((opcode & 0x07f07000) == 0x07f02000) {
		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		strcpy(cp, "UNDEFINED");
		return ERROR_OK;
	}

	switch ((opcode >> 12) & 0x5) {
	case 0x1:
	case 0x5:
		return t2ev_b_bl(opcode, address, instruction, cp);
	case 0x4:
		goto undef;
	case 0:
		if (((opcode >> 23) & 0x07) != 0x07)
			return t2ev_cond_b(opcode, address, instruction, cp);
		if (opcode & (1 << 26))
			goto undef;
		break;
	}

	switch ((opcode >> 20) & 0x7f) {
	case 0x38:
	case 0x39:
		sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff),
				(int) (opcode >> 16) & 0x0f);
		return ERROR_OK;
	case 0x3a:
		return t2ev_hint(opcode, address, instruction, cp);
	case 0x3b:
		return t2ev_misc(opcode, address, instruction, cp);
	case 0x3c:
		sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f);
		return ERROR_OK;
	case 0x3e:
	case 0x3f:
		sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f,
				special_name(opcode & 0xff));
		return ERROR_OK;
	}

undef:
	return ERROR_INVALID_ARGUMENTS;
}

static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	char *mnemonic = NULL;
	int rn = (opcode >> 16) & 0xf;
	int rd = (opcode >> 8) & 0xf;
	unsigned immed = opcode & 0xff;
	unsigned func;
	bool one = false;
	char *suffix = "";
	char *suffix2 = "";

	/* ARMv7-M: A5.3.2 Modified immediate constants */
	func = (opcode >> 11) & 0x0e;
	if (immed & 0x80)
		func |= 1;
	if (opcode & (1 << 26))
		func |= 0x10;

	/* "Modified" immediates */
	switch (func >> 1) {
	case 0:
		break;
	case 2:
		immed <<= 8;
		/* FALLTHROUGH */
	case 1:
		immed += immed << 16;
		break;
	case 3:
		immed += immed << 8;
		immed += immed << 16;
		break;
	default:
		immed |= 0x80;
		immed = ror(immed, func);
	}

	if (opcode & (1 << 20))
		suffix = "S";

	switch ((opcode >> 21) & 0xf) {
	case 0:
		if (rd == 0xf) {
			instruction->type = ARM_TST;
			mnemonic = "TST";
			one = true;
			suffix = "";
			rd = rn;
		} else {
			instruction->type = ARM_AND;
			mnemonic = "AND";
		}
		break;
	case 1:
		instruction->type = ARM_BIC;
		mnemonic = "BIC";
		break;
	case 2:
		if (rn == 0xf) {
			instruction->type = ARM_MOV;
			mnemonic = "MOV";
			one = true;
			suffix2 = ".W";
		} else {
			instruction->type = ARM_ORR;
			mnemonic = "ORR";
		}
		break;
	case 3:
		if (rn == 0xf) {
			instruction->type = ARM_MVN;
			mnemonic = "MVN";
			one = true;
		} else {
			// instruction->type = ARM_ORN;
			mnemonic = "ORN";
		}
		break;
	case 4:
		if (rd == 0xf) {
			instruction->type = ARM_TEQ;
			mnemonic = "TEQ";
			one = true;
			suffix = "";
			rd = rn;
		} else {
			instruction->type = ARM_EOR;
			mnemonic = "EOR";
		}
		break;
	case 8:
		if (rd == 0xf) {
			instruction->type = ARM_CMN;
			mnemonic = "CMN";
			one = true;
			suffix = "";
			rd = rn;
		} else {
			instruction->type = ARM_ADD;
			mnemonic = "ADD";
			suffix2 = ".W";
		}
		break;
	case 10:
		instruction->type = ARM_ADC;
		mnemonic = "ADC";
		suffix2 = ".W";
		break;
	case 11:
		instruction->type = ARM_SBC;
		mnemonic = "SBC";
		break;
	case 13:
		if (rd == 0xf) {
			instruction->type = ARM_CMP;
			mnemonic = "CMP";
			one = true;
			suffix = "";
			rd = rn;
		} else {
			instruction->type = ARM_SUB;
			mnemonic = "SUB";
		}
		suffix2 = ".W";
		break;
	case 14:
		instruction->type = ARM_RSB;
		mnemonic = "RSB";
		suffix2 = ".W";
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	if (one)
		sprintf(cp, "%s%s\tr%d, #%d\t; %#8.8x",
				mnemonic, suffix2 ,rd, immed, immed);
	else
		sprintf(cp, "%s%s%s\tr%d, r%d, #%d\t; %#8.8x",
				mnemonic, suffix, suffix2,
				rd, rn, immed, immed);

	return ERROR_OK;
}

static int t2ev_data_immed(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	char *mnemonic = NULL;
	int rn = (opcode >> 16) & 0xf;
	int rd = (opcode >> 8) & 0xf;
	unsigned immed;
	bool add = false;
	bool is_signed = false;

	immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4);
	if (opcode & (1 << 26))
		immed |= (1 << 11);

	switch ((opcode >> 20) & 0x1f) {
	case 0:
		if (rn == 0xf) {
			add = true;
			goto do_adr;
		}
		mnemonic = "ADDW";
		break;
	case 4:
		immed |= (opcode >> 4) & 0xf000;
		sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed);
		return ERROR_OK;
	case 0x0a:
		if (rn == 0xf)
			goto do_adr;
		mnemonic = "SUBW";
		break;
	case 0x0c:
		/* move constant to top 16 bits of register */
		immed |= (opcode >> 4) & 0xf000;
		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
		return ERROR_OK;
	case 0x10:
	case 0x12:
		is_signed = true;
	case 0x18:
	case 0x1a:
		/* signed/unsigned saturated add */
		immed = (opcode >> 6) & 0x03;
		immed |= (opcode >> 10) & 0x1c;
		sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
				is_signed ? "S" : "U",
				rd, (int) (opcode & 0x1f) + is_signed, rn,
				(opcode & (1 << 21)) ? "ASR" : "LSL",
				immed ? immed : 32);
		return ERROR_OK;
	case 0x14:
		is_signed = true;
		/* FALLTHROUGH */
	case 0x1c:
		/* signed/unsigned bitfield extract */
		immed = (opcode >> 6) & 0x03;
		immed |= (opcode >> 10) & 0x1c;
		sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t",
				is_signed ? "S" : "U",
				rd, rn, immed,
				(int) (opcode & 0x1f) + 1);
		return ERROR_OK;
	case 0x16:
		immed = (opcode >> 6) & 0x03;
		immed |= (opcode >> 10) & 0x1c;
		if (rn == 0xf)		/* bitfield clear */
			sprintf(cp, "BFC\tr%d, #%d, #%d\t",
					rd, immed,
					(int) (opcode & 0x1f) + 1 - immed);
		else			/* bitfield insert */
			sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t",
					rd, rn, immed,
					(int) (opcode & 0x1f) + 1 - immed);
		return ERROR_OK;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	sprintf(cp, "%s\tr%d, r%d, #%d\t; %#3.3x", mnemonic,
			rd, rn, immed, immed);
	return ERROR_OK;

do_adr:
	address = thumb_alignpc4(address);
	if (add)
		address += immed;
	else
		address -= immed;
	/* REVISIT "ADD/SUB Rd, PC, #const ; 0x..." might be better;
	 * not hiding the pc-relative stuff will sometimes be useful.
	 */
	sprintf(cp, "ADR.W\tr%d, %#8.8" PRIx32, rd, address);
	return ERROR_OK;
}

static int t2ev_store_single(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	unsigned op = (opcode >> 20) & 0xf;
	char *size = "";
	char *suffix = "";
	char *p1 = "";
	char *p2 = "]";
	unsigned immed;
	unsigned rn = (opcode >> 16) & 0x0f;
	unsigned rt = (opcode >> 12) & 0x0f;

	if (rn == 0xf)
		return ERROR_INVALID_ARGUMENTS;

	if (opcode & 0x0800)
		op |= 1;
	switch (op) {
	/* byte */
	case 0x8:
	case 0x9:
		size = "B";
		goto imm12;
	case 0x1:
		size = "B";
		goto imm8;
	case 0x0:
		size = "B";
		break;
	/* halfword */
	case 0xa:
	case 0xb:
		size = "H";
		goto imm12;
	case 0x3:
		size = "H";
		goto imm8;
	case 0x2:
		size = "H";
		break;
	/* word */
	case 0xc:
	case 0xd:
		goto imm12;
	case 0x5:
		goto imm8;
	case 0x4:
		break;
	/* error */
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
			size, rt, rn, (int) opcode & 0x0f,
			(int) (opcode >> 4) & 0x03);
	return ERROR_OK;

imm12:
	immed = opcode & 0x0fff;
	sprintf(cp, "STR%s.W\tr%d, [r%d, #%u]\t; %#3.3x",
			size, rt, rn, immed, immed);
	return ERROR_OK;

imm8:
	immed = opcode & 0x00ff;

	switch (opcode & 0x700) {
	case 0x600:
		suffix = "T";
		break;
	case 0x000:
	case 0x200:
		return ERROR_INVALID_ARGUMENTS;
	}

	/* two indexed modes will write back rn */
	if (opcode & 0x100) {
		if (opcode & 0x400)	/* pre-indexed */
			p2 = "]!";
		else {			/* post-indexed */
			p1 = "]";
			p2 = "";
		}
	}

	sprintf(cp, "STR%s%s\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
			size, suffix, rt, rn, p1,
			(opcode & 0x200) ? "" : "-",
			immed, p2, immed);
	return ERROR_OK;
}

static int t2ev_mul32(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int ra = (opcode >> 12) & 0xf;

	switch (opcode & 0x007000f0) {
	case 0:
		if (ra == 0xf)
			sprintf(cp, "MUL\tr%d, r%d, r%d",
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf);
		else
			sprintf(cp, "MLA\tr%d, r%d, r%d, r%d",
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf, ra);
		break;
	case 0x10:
		sprintf(cp, "MLS\tr%d, r%d, r%d, r%d",
			(int) (opcode >> 8) & 0xf,
			(int) (opcode >> 16) & 0xf,
			(int) (opcode >> 0) & 0xf, ra);
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}
	return ERROR_OK;
}

static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int op = (opcode >> 4) & 0xf;
	char *infix = "MUL";

	op += (opcode >> 16) & 0x70;
	switch (op) {
	case 0x40:
	case 0x60:
		infix = "MLA";
		/* FALLTHROUGH */
	case 0:
	case 0x20:
		sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d",
				(op & 0x20) ? 'U' : 'S',
				infix,
				(int) (opcode >> 12) & 0xf,
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf);
		break;
	case 0x1f:
	case 0x3f:
		sprintf(cp, "%cDIV\tr%d, r%d, r%d",
				(op & 0x20) ? 'U' : 'S',
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf);
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	return ERROR_OK;
}

static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int rn = (opcode >> 16) & 0xf;
	int op = (opcode >> 22) & 0x6;
	int t = (opcode >> 21) & 1;
	unsigned registers = opcode & 0xffff;

	if (opcode & (1 << 20))
		op |= 1;

	switch (op) {
	case 2:
		sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
		break;
	case 3:
		if (rn == 13 && t)
			sprintf(cp, "POP.W\t");
		else
			sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
		break;
	case 4:
		if (rn == 13 && t)
			sprintf(cp, "PUSH.W\t");
		else
			sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : "");
		break;
	case 5:
		sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	cp = strchr(cp, 0);
	*cp++ = '{';
	for (t = 0; registers; t++, registers >>= 1) {
		if ((registers & 1) == 0)
			continue;
		registers &= ~1;
		sprintf(cp, "r%d%s", t, registers ? ", " : "");
		cp = strchr(cp, 0);
	}
	*cp++ = '}';
	*cp++ = 0;

	return ERROR_OK;
}

/* load/store dual or exclusive, table branch */
static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	unsigned op1op2 = (opcode >> 20) & 0x3;
	unsigned op3 = (opcode >> 4) & 0xf;
	char *mnemonic;
	unsigned rn = (opcode >> 16) & 0xf;
	unsigned rt = (opcode >> 12) & 0xf;
	unsigned rd = (opcode >> 8) & 0xf;
	unsigned imm = opcode & 0xff;
	char *p1 = "";
	char *p2 = "]";

	op1op2 |= (opcode >> 21) & 0xc;
	switch (op1op2) {
	case 0:
		mnemonic = "STREX";
		goto strex;
	case 1:
		mnemonic = "LDREX";
		goto ldrex;
	case 2:
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
		mnemonic = "STRD";
		goto immediate;
	case 3:
	case 7:
	case 9:
	case 11:
	case 13:
	case 15:
		mnemonic = "LDRD";
		if (rn == 15)
			goto literal;
		else
			goto immediate;
	case 4:
		switch (op3) {
		case 4:
			mnemonic = "STREXB";
			break;
		case 5:
			mnemonic = "STREXH";
			break;
		default:
			return ERROR_INVALID_ARGUMENTS;
		}
		rd = opcode & 0xf;
		imm = 0;
		goto strex;
	case 5:
		switch (op3) {
		case 0:
			sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf);
			return ERROR_OK;
		case 1:
			sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf);
			return ERROR_OK;
		case 4:
			mnemonic = "LDREXB";
			break;
		case 5:
			mnemonic = "LDREXH";
			break;
		default:
			return ERROR_INVALID_ARGUMENTS;
		}
		imm = 0;
		goto ldrex;
	}
	return ERROR_INVALID_ARGUMENTS;

strex:
	imm <<= 2;
	if (imm)
		sprintf(cp, "%s\tr%u, r%u, [r%u, #%u]\t; %#2.2x",
				mnemonic, rd, rt, rn, imm, imm);
	else
		sprintf(cp, "%s\tr%u, r%u, [r%u]",
				mnemonic, rd, rt, rn);
	return ERROR_OK;

ldrex:
	imm <<= 2;
	if (imm)
		sprintf(cp, "%s\tr%u, [r%u, #%u]\t; %#2.2x",
				mnemonic, rt, rn, imm, imm);
	else
		sprintf(cp, "%s\tr%u, [r%u]",
				mnemonic, rt, rn);
	return ERROR_OK;

immediate:
	/* two indexed modes will write back rn */
	if (opcode & (1 << 21)) {
		if (opcode & (1 << 24))	/* pre-indexed */
			p2 = "]!";
		else {			/* post-indexed */
			p1 = "]";
			p2 = "";
		}
	}

	imm <<= 2;
	sprintf(cp, "%s\tr%u, r%u, [r%u%s, #%s%u%s\t; %#2.2x",
			mnemonic, rt, rd, rn, p1,
			(opcode & (1 << 23)) ? "" : "-",
			imm, p2, imm);
	return ERROR_OK;

literal:
	address = thumb_alignpc4(address);
	imm <<= 2;
	if (opcode & (1 << 23))
		address += imm;
	else
		address -= imm;
	sprintf(cp, "%s\tr%u, r%u, %#8.8" PRIx32,
			mnemonic, rt, rd, address);
	return ERROR_OK;
}

static int t2ev_data_shift(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int op = (opcode >> 21) & 0xf;
	int rd = (opcode >> 8) & 0xf;
	int rn = (opcode >> 16) & 0xf;
	int type = (opcode >> 4) & 0x3;
	int immed = (opcode >> 6) & 0x3;
	char *mnemonic;
	char *suffix = "";

	immed |= (opcode >> 10) & 0x1c;
	if (opcode & (1 << 20))
		suffix = "S";

	switch (op) {
	case 0:
		if (rd == 0xf) {
			if (!(opcode & (1 << 20)))
				return ERROR_INVALID_ARGUMENTS;
			instruction->type = ARM_TST;
			mnemonic = "TST";
			suffix = "";
			goto two;
		}
		instruction->type = ARM_AND;
		mnemonic = "AND";
		break;
	case 1:
		instruction->type = ARM_BIC;
		mnemonic = "BIC";
		break;
	case 2:
		if (rn == 0xf) {
			instruction->type = ARM_MOV;
			switch (type) {
			case 0:
				if (immed == 0) {
					sprintf(cp, "MOV%s.W\tr%d, r%d",
						suffix, rd,
						(int) (opcode & 0xf));
					return ERROR_OK;
				}
				mnemonic = "LSL";
				break;
			case 1:
				mnemonic = "LSR";
				break;
			case 2:
				mnemonic = "ASR";
				break;
			default:
				if (immed == 0) {
					sprintf(cp, "RRX%s\tr%d, r%d",
						suffix, rd,
						(int) (opcode & 0xf));
					return ERROR_OK;
				}
				mnemonic = "ROR";
				break;
			}
			goto immediate;
		} else {
			instruction->type = ARM_ORR;
			mnemonic = "ORR";
		}
		break;
	case 3:
		if (rn == 0xf) {
			instruction->type = ARM_MVN;
			mnemonic = "MVN";
			rn = rd;
			goto two;
		} else {
			// instruction->type = ARM_ORN;
			mnemonic = "ORN";
		}
		break;
	case 4:
		if (rd == 0xf) {
			if (!(opcode & (1 << 20)))
				return ERROR_INVALID_ARGUMENTS;
			instruction->type = ARM_TEQ;
			mnemonic = "TEQ";
			suffix = "";
			goto two;
		}
		instruction->type = ARM_EOR;
		mnemonic = "EOR";
		break;
	case 8:
		if (rd == 0xf) {
			if (!(opcode & (1 << 20)))
				return ERROR_INVALID_ARGUMENTS;
			instruction->type = ARM_CMN;
			mnemonic = "CMN";
			suffix = "";
			goto two;
		}
		instruction->type = ARM_ADD;
		mnemonic = "ADD";
		break;
	case 0xa:
		instruction->type = ARM_ADC;
		mnemonic = "ADC";
		break;
	case 0xb:
		instruction->type = ARM_SBC;
		mnemonic = "SBC";
		break;
	case 0xd:
		if (rd == 0xf) {
			if (!(opcode & (1 << 21)))
				return ERROR_INVALID_ARGUMENTS;
			instruction->type = ARM_CMP;
			mnemonic = "CMP";
			suffix = "";
			goto two;
		}
		instruction->type = ARM_SUB;
		mnemonic = "SUB";
		break;
	case 0xe:
		instruction->type = ARM_RSB;
		mnemonic = "RSB";
		break;
	default:
		return ERROR_INVALID_ARGUMENTS;
	}

	sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
		mnemonic, suffix, rd, rn, (int) (opcode & 0xf));

shift:
	cp = strchr(cp, 0);

	switch (type) {
	case 0:
		if (immed == 0)
			return ERROR_OK;
		suffix = "LSL";
		break;
	case 1:
		suffix = "LSR";
		if (immed == 32)
			immed = 0;
		break;
	case 2:
		suffix = "ASR";
		if (immed == 32)
			immed = 0;
		break;
	case 3:
		if (immed == 0) {
			strcpy(cp, ", RRX");
			return ERROR_OK;
		}
		suffix = "ROR";
		break;
	}
	sprintf(cp, ", %s #%d", suffix, immed ? immed : 32);
	return ERROR_OK;

two:
	sprintf(cp, "%s%s.W\tr%d, r%d",
		mnemonic, suffix, rn, (int) (opcode & 0xf));
	goto shift;

immediate:
	sprintf(cp, "%s%s.W\tr%d, r%d, #%d",
		mnemonic, suffix, rd,
		(int) (opcode & 0xf), immed ? immed : 32);
	return ERROR_OK;
}

static int t2ev_data_reg(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	char *mnemonic;
	char * suffix = "";

	if (((opcode >> 4) & 0xf) == 0) {
		switch ((opcode >> 21) & 0x7) {
		case 0:
			mnemonic = "LSL";
			break;
		case 1:
			mnemonic = "LSR";
			break;
		case 2:
			mnemonic = "ASR";
			break;
		case 3:
			mnemonic = "ROR";
			break;
		default:
			return ERROR_INVALID_ARGUMENTS;
		}

		instruction->type = ARM_MOV;
		if (opcode & (1 << 20))
			suffix = "S";
		sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
				mnemonic, suffix,
				(int) (opcode >> 8) & 0xf,
				(int) (opcode >> 16) & 0xf,
				(int) (opcode >> 0) & 0xf);

	} else if (opcode & (1 << 7)) {
		switch ((opcode >> 20) & 0xf) {
		case 0:
		case 1:
		case 4:
		case 5:
			switch ((opcode >> 4) & 0x3) {
			case 1:
				suffix = ", ROR #8";
				break;
			case 2:
				suffix = ", ROR #16";
				break;
			case 3:
				suffix = ", ROR #24";
				break;
			}
			sprintf(cp, "%cXT%c.W\tr%d, r%d%s",
					(opcode & (1 << 24)) ? 'U' : 'S',
					(opcode & (1 << 26)) ? 'B' : 'H',
					(int) (opcode >> 8) & 0xf,
					(int) (opcode >> 0) & 0xf,
					suffix);
			break;
		case 8:
		case 9:
		case 0xa:
		case 0xb:
			if (opcode & (1 << 6))
				return ERROR_INVALID_ARGUMENTS;
			if (((opcode >> 12) & 0xf) != 0xf)
				return ERROR_INVALID_ARGUMENTS;
			if (!(opcode & (1 << 20)))
				return ERROR_INVALID_ARGUMENTS;

			switch (((opcode >> 19) & 0x04)
				| ((opcode >> 4) & 0x3)) {
			case 0:
				mnemonic = "REV.W";
				break;
			case 1:
				mnemonic = "REV16.W";
				break;
			case 2:
				mnemonic = "RBIT";
				break;
			case 3:
				mnemonic = "REVSH.W";
				break;
			case 4:
				mnemonic = "CLZ";
				break;
			default:
				return ERROR_INVALID_ARGUMENTS;
			}
			sprintf(cp, "%s\tr%d, r%d",
					mnemonic,
					(int) (opcode >> 8) & 0xf,
					(int) (opcode >> 0) & 0xf);
			break;
		default:
			return ERROR_INVALID_ARGUMENTS;
		}
	}

	return ERROR_OK;
}

static int t2ev_load_word(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int rn = (opcode >> 16) & 0xf;
	int immed;

	instruction->type = ARM_LDR;

	if (rn == 0xf) {
		immed = opcode & 0x0fff;
		if ((opcode & (1 << 23)) == 0)
			immed = -immed;
		sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
				(int) (opcode >> 12) & 0xf,
				thumb_alignpc4(address) + immed);
		return ERROR_OK;
	}

	if (opcode & (1 << 23)) {
		immed = opcode & 0x0fff;
		sprintf(cp, "LDR.W\tr%d, [r%d, #%d]\t; %#3.3x",
				(int) (opcode >> 12) & 0xf,
				rn, immed, immed);
		return ERROR_OK;
	}

	if (!(opcode & (0x3f << 6))) {
		sprintf(cp, "LDR.W\tr%d, [r%d, r%d, LSL #%d]",
				(int) (opcode >> 12) & 0xf,
				rn,
				(int) (opcode >> 0) & 0xf,
				(int) (opcode >> 4) & 0x3);
		return ERROR_OK;
	}


	if (((opcode >> 8) & 0xf) == 0xe) {
		immed = opcode & 0x00ff;

		sprintf(cp, "LDRT\tr%d, [r%d, #%d]\t; %#2.2x",
				(int) (opcode >> 12) & 0xf,
				rn, immed, immed);
		return ERROR_OK;
	}

	if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
		char *p1 = "]", *p2 = "";

		if (!(opcode & 0x0500))
			return ERROR_INVALID_ARGUMENTS;

		immed = opcode & 0x00ff;

		/* two indexed modes will write back rn */
		if (opcode & 0x100) {
			if (opcode & 0x400)	/* pre-indexed */
				p2 = "]!";
			else {			/* post-indexed */
				p1 = "]";
				p2 = "";
			}
		}

		sprintf(cp, "LDR\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
				(int) (opcode >> 12) & 0xf,
				rn, p1,
				(opcode & 0x200) ? "" : "-",
				immed, p2, immed);
		return ERROR_OK;
	}

	return ERROR_INVALID_ARGUMENTS;
}

static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int rn = (opcode >> 16) & 0xf;
	int rt = (opcode >> 12) & 0xf;
	int op2 = (opcode >> 6) & 0x3f;
	unsigned immed;
	char *p1 = "", *p2 = "]";
	char *mnemonic;

	switch ((opcode >> 23) & 0x3) {
	case 0:
		if ((rn & rt) == 0xf) {
pld_literal:
			immed = opcode & 0xfff;
			address = thumb_alignpc4(address);
			if (opcode & (1 << 23))
				address += immed;
			else
				address -= immed;
			sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
					rt, address);
			return ERROR_OK;
		}
		if (rn == 0x0f && rt != 0x0f) {
ldrb_literal:
			immed = opcode & 0xfff;
			address = thumb_alignpc4(address);
			if (opcode & (1 << 23))
				address += immed;
			else
				address -= immed;
			sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32,
					rt, address);
			return ERROR_OK;
		}
		if (rn == 0x0f)
			break;
		if ((op2 & 0x3c) == 0x38) {
			immed = opcode & 0xff;
			sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x",
					rt, rn, immed, immed);
			return ERROR_OK;
		}
		if ((op2 & 0x3c) == 0x30) {
			if (rt == 0x0f) {
				immed = opcode & 0xff;
				immed = -immed;
preload_immediate:
				p1 = (opcode & (1 << 21)) ? "W" : "";
				sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
						p1, rn, immed, immed);
				return ERROR_OK;
			}
			mnemonic = "LDRB";
ldrxb_immediate_t3:
			immed = opcode & 0xff;
			if (!(opcode & 0x200))
				immed = -immed;

			/* two indexed modes will write back rn */
			if (opcode & 0x100) {
				if (opcode & 0x400)	/* pre-indexed */
					p2 = "]!";
				else {			/* post-indexed */
					p1 = "]";
					p2 = "";
				}
			}
ldrxb_immediate_t2:
			sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x",
					mnemonic, rt, rn, p1,
					immed, p2, immed);
			return ERROR_OK;
		}
		if ((op2 & 0x24) == 0x24) {
			mnemonic = "LDRB";
			goto ldrxb_immediate_t3;
		}
		if (op2 == 0) {
			int rm = opcode & 0xf;

			if (rt == 0x0f)
				sprintf(cp, "PLD\t");
			else
				sprintf(cp, "LDRB.W\tr%d, ", rt);
			immed = (opcode >> 4) & 0x3;
			cp = strchr(cp, 0);
			sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
			return ERROR_OK;
		}
		break;
	case 1:
		if ((rn & rt) == 0xf)
			goto pld_literal;
		if (rt == 0xf) {
			immed = opcode & 0xfff;
			goto preload_immediate;
		}
		if (rn == 0x0f)
			goto ldrb_literal;
		mnemonic = "LDRB.W";
		immed = opcode & 0xfff;
		goto ldrxb_immediate_t2;
	case 2:
		if ((rn & rt) == 0xf) {
			immed = opcode & 0xfff;
			address = thumb_alignpc4(address);
			if (opcode & (1 << 23))
				address += immed;
			else
				address -= immed;
			sprintf(cp, "PLI\t%#8.8" PRIx32, address);
			return ERROR_OK;
		}
		if (rn == 0xf && rt != 0xf) {
ldrsb_literal:
			immed = opcode & 0xfff;
			address = thumb_alignpc4(address);
			if (opcode & (1 << 23))
				address += immed;
			else
				address -= immed;
			sprintf(cp, "LDRSB\t%#8.8" PRIx32, address);
			return ERROR_OK;
		}
		if (rn == 0xf)
			break;
		if ((op2 & 0x3c) == 0x38) {
			immed = opcode & 0xff;
			sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
					rt, rn, immed, immed);
			return ERROR_OK;
		}
		if ((op2 & 0x3c) == 0x30) {
			if (rt == 0xf) {
				immed = opcode & 0xff;
				immed = -immed;	// pli
				sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
						rn, immed, -immed);
				return ERROR_OK;
			}
			mnemonic = "LDRSB";
			goto ldrxb_immediate_t3;
		}
		if ((op2 & 0x24) == 0x24) {
			mnemonic = "LDRSB";
			goto ldrxb_immediate_t3;
		}
		if (op2 == 0) {
			int rm = opcode & 0xf;

			if (rt == 0x0f)
				sprintf(cp, "PLI\t");
			else
				sprintf(cp, "LDRSB.W\tr%d, ", rt);
			immed = (opcode >> 4) & 0x3;
			cp = strchr(cp, 0);
			sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
			return ERROR_OK;
		}
		break;
	case 3:
		if (rt == 0xf) {
			immed = opcode & 0xfff;
			sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x",
					rn, immed, immed);
			return ERROR_OK;
		}
		if (rn == 0xf)
			goto ldrsb_literal;
		immed = opcode & 0xfff;
		mnemonic = "LDRSB";
		goto ldrxb_immediate_t2;
	}

	return ERROR_INVALID_ARGUMENTS;
}

static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
		arm_instruction_t *instruction, char *cp)
{
	int rn = (opcode >> 16) & 0xf;
	int rt = (opcode >> 12) & 0xf;
	int op2 = (opcode >> 6) & 0x3f;
	char *sign = "";
	unsigned immed;

	if (rt == 0xf) {
		sprintf(cp, "HINT (UNALLOCATED)");
		return ERROR_OK;
	}

	if (opcode & (1 << 24))
		sign = "S";

	if ((opcode & (1 << 23)) == 0) {
		if (rn == 0xf) {
ldrh_literal:
			immed = opcode & 0xfff;
			address = thumb_alignpc4(address);
			if (opcode & (1 << 23))
				address += immed;
			else
				address -= immed;
			sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32,
					sign, rt, address);
			return ERROR_OK;
		}
		if (op2 == 0) {
			int rm = opcode & 0xf;

			immed = (opcode >> 4) & 0x3;
			sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]",
					sign, rt, rn, rm, immed);
			return ERROR_OK;
		}
		if ((op2 & 0x3c) == 0x38) {
			immed = opcode & 0xff;
			sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
					sign, rt, rn, immed, immed);
			return ERROR_OK;
		}
		if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
			char *p1 = "", *p2 = "]";

			immed = opcode & 0xff;
			if (!(opcode & 0x200))
				immed = -immed;

			/* two indexed modes will write back rn */
			if (opcode & 0x100) {
				if (opcode & 0x400)	/* pre-indexed */
					p2 = "]!";
				else {			/* post-indexed */
					p1 = "]";
					p2 = "";
				}
			}
			sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x",
					sign, rt, rn, p1, immed, p2, immed);
			return ERROR_OK;
		}
	} else {
		if (rn == 0xf)
			goto ldrh_literal;

		immed = opcode & 0xfff;
		sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
				sign, *sign ? "" : ".W",
				rt, rn, immed, immed);
		return ERROR_OK;
	}

	return ERROR_INVALID_ARGUMENTS;
}

/*
 * REVISIT for Thumb2 instructions, instruction->type and friends aren't
 * always set.  That means eventual arm_simulate_step() support for Thumb2
 * will need work in this area.
 */
int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruction)
{
	int retval;
	uint16_t op;
	uint32_t opcode;
	char *cp;

	/* clear low bit ... it's set on function pointers */
	address &= ~1;

	/* clear fields, to avoid confusion */
	memset(instruction, 0, sizeof(arm_instruction_t));

	/* read first halfword, see if this is the only one */
	retval = target_read_u16(target, address, &op);
	if (retval != ERROR_OK)
		return retval;

	switch (op & 0xf800) {
	case 0xf800:
	case 0xf000:
	case 0xe800:
		/* 32-bit instructions */
		instruction->instruction_size = 4;
		opcode = op << 16;
		retval = target_read_u16(target, address + 2, &op);
		if (retval != ERROR_OK)
			return retval;
		opcode |= op;
		instruction->opcode = opcode;
		break;
	default:
		/* 16-bit:  Thumb1 + IT + CBZ/CBNZ + ... */
		return thumb_evaluate_opcode(op, address, instruction);
	}

	snprintf(instruction->text, 128,
			"0x%8.8" PRIx32 "  0x%8.8" PRIx32 "\t",
			address, opcode);
	cp = strchr(instruction->text, 0);
	retval = ERROR_FAIL;

	/* ARMv7-M: A5.3.1 Data processing (modified immediate) */
	if ((opcode & 0x1a008000) == 0x10000000)
		retval = t2ev_data_mod_immed(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.3 Data processing (plain binary immediate) */
	else if ((opcode & 0x1a008000) == 0x12000000)
		retval = t2ev_data_immed(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
	else if ((opcode & 0x18008000) == 0x10008000)
		retval = t2ev_b_misc(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.5 Load/store multiple */
	else if ((opcode & 0x1e400000) == 0x08000000)
		retval = t2ev_ldm_stm(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch */
	else if ((opcode & 0x1e400000) == 0x08400000)
		retval = t2ev_ldrex_strex(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.7 Load word */
	else if ((opcode & 0x1f700000) == 0x18500000)
		retval = t2ev_load_word(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
	else if ((opcode & 0x1e700000) == 0x18300000)
		retval = t2ev_load_halfword(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.9 Load byte, memory hints */
	else if ((opcode & 0x1e700000) == 0x18100000)
		retval = t2ev_load_byte_hints(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.10 Store single data item */
	else if ((opcode & 0x1f100000) == 0x18000000)
		retval = t2ev_store_single(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.11 Data processing (shifted register) */
	else if ((opcode & 0x1e000000) == 0x0a000000)
		retval = t2ev_data_shift(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.12 Data processing (register)
	 * and      A5.3.13 Miscellaneous operations
	 */
	else if ((opcode & 0x1f000000) == 0x1a000000)
		retval = t2ev_data_reg(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */
	else if ((opcode & 0x1f800000) == 0x1b000000)
		retval = t2ev_mul32(opcode, address, instruction, cp);

	/* ARMv7-M: A5.3.15 Long multiply, long multiply accumulate, divide */
	else if ((opcode & 0x1f800000) == 0x1b800000)
		retval = t2ev_mul64_div(opcode, address, instruction, cp);

	if (retval == ERROR_OK)
		return retval;

	/*
	 * Thumb2 also supports coprocessor, ThumbEE, and DSP/Media (SIMD)
	 * instructions; not yet handled here.
	 */

	if (retval == ERROR_INVALID_ARGUMENTS) {
		instruction->type = ARM_UNDEFINED_INSTRUCTION;
		strcpy(cp, "UNDEFINED OPCODE");
		return ERROR_OK;
	}

	LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08" PRIx32 ")",
			opcode);

	strcpy(cp, "(32-bit Thumb2 ...)");
	return ERROR_OK;
}

int arm_access_size(arm_instruction_t *instruction)
{
	if ((instruction->type == ARM_LDRB)
		|| (instruction->type == ARM_LDRBT)
		|| (instruction->type == ARM_LDRSB)
		|| (instruction->type == ARM_STRB)
		|| (instruction->type == ARM_STRBT))
	{
		return 1;
	}
	else if ((instruction->type == ARM_LDRH)
		|| (instruction->type == ARM_LDRSH)
		|| (instruction->type == ARM_STRH))
	{
		return 2;
	}
	else if ((instruction->type == ARM_LDR)
		|| (instruction->type == ARM_LDRT)
		|| (instruction->type == ARM_STR)
		|| (instruction->type == ARM_STRT))
	{
		return 4;
	}
	else if ((instruction->type == ARM_LDRD)
		|| (instruction->type == ARM_STRD))
	{
		return 8;
	}
	else
	{
		LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
		return 0;
	}
}
7</a>
<a id='n2808' href='#n2808'>2808</a>
<a id='n2809' href='#n2809'>2809</a>
<a id='n2810' href='#n2810'>2810</a>
<a id='n2811' href='#n2811'>2811</a>
<a id='n2812' href='#n2812'>2812</a>
<a id='n2813' href='#n2813'>2813</a>
<a id='n2814' href='#n2814'>2814</a>
<a id='n2815' href='#n2815'>2815</a>
<a id='n2816' href='#n2816'>2816</a>
<a id='n2817' href='#n2817'>2817</a>
<a id='n2818' href='#n2818'>2818</a>
<a id='n2819' href='#n2819'>2819</a>
<a id='n2820' href='#n2820'>2820</a>
<a id='n2821' href='#n2821'>2821</a>
<a id='n2822' href='#n2822'>2822</a>
<a id='n2823' href='#n2823'>2823</a>
<a id='n2824' href='#n2824'>2824</a>
<a id='n2825' href='#n2825'>2825</a>
<a id='n2826' href='#n2826'>2826</a>
<a id='n2827' href='#n2827'>2827</a>
<a id='n2828' href='#n2828'>2828</a>
<a id='n2829' href='#n2829'>2829</a>
<a id='n2830' href='#n2830'>2830</a>
<a id='n2831' href='#n2831'>2831</a>
<a id='n2832' href='#n2832'>2832</a>
<a id='n2833' href='#n2833'>2833</a>
<a id='n2834' href='#n2834'>2834</a>
<a id='n2835' href='#n2835'>2835</a>
<a id='n2836' href='#n2836'>2836</a>
<a id='n2837' href='#n2837'>2837</a>
<a id='n2838' href='#n2838'>2838</a>
<a id='n2839' href='#n2839'>2839</a>
<a id='n2840' href='#n2840'>2840</a>
<a id='n2841' href='#n2841'>2841</a>
<a id='n2842' href='#n2842'>2842</a>
<a id='n2843' href='#n2843'>2843</a>
<a id='n2844' href='#n2844'>2844</a>
<a id='n2845' href='#n2845'>2845</a>
<a id='n2846' href='#n2846'>2846</a>
<a id='n2847' href='#n2847'>2847</a>
<a id='n2848' href='#n2848'>2848</a>
<a id='n2849' href='#n2849'>2849</a>
<a id='n2850' href='#n2850'>2850</a>
<a id='n2851' href='#n2851'>2851</a>
<a id='n2852' href='#n2852'>2852</a>
<a id='n2853' href='#n2853'>2853</a>
<a id='n2854' href='#n2854'>2854</a>
<a id='n2855' href='#n2855'>2855</a>
<a id='n2856' href='#n2856'>2856</a>
<a id='n2857' href='#n2857'>2857</a>
<a id='n2858' href='#n2858'>2858</a>
<a id='n2859' href='#n2859'>2859</a>
<a id='n2860' href='#n2860'>2860</a>
<a id='n2861' href='#n2861'>2861</a>
<a id='n2862' href='#n2862'>2862</a>
<a id='n2863' href='#n2863'>2863</a>
<a id='n2864' href='#n2864'>2864</a>
<a id='n2865' href='#n2865'>2865</a>
<a id='n2866' href='#n2866'>2866</a>
<a id='n2867' href='#n2867'>2867</a>
<a id='n2868' href='#n2868'>2868</a>
<a id='n2869' href='#n2869'>2869</a>
<a id='n2870' href='#n2870'>2870</a>
<a id='n2871' href='#n2871'>2871</a>
<a id='n2872' href='#n2872'>2872</a>
<a id='n2873' href='#n2873'>2873</a>
<a id='n2874' href='#n2874'>2874</a>
<a id='n2875' href='#n2875'>2875</a>
<a id='n2876' href='#n2876'>2876</a>
<a id='n2877' href='#n2877'>2877</a>
<a id='n2878' href='#n2878'>2878</a>
<a id='n2879' href='#n2879'>2879</a>
<a id='n2880' href='#n2880'>2880</a>
<a id='n2881' href='#n2881'>2881</a>
<a id='n2882' href='#n2882'>2882</a>
<a id='n2883' href='#n2883'>2883</a>
<a id='n2884' href='#n2884'>2884</a>
<a id='n2885' href='#n2885'>2885</a>
<a id='n2886' href='#n2886'>2886</a>
<a id='n2887' href='#n2887'>2887</a>
<a id='n2888' href='#n2888'>2888</a>
<a id='n2889' href='#n2889'>2889</a>
<a id='n2890' href='#n2890'>2890</a>
<a id='n2891' href='#n2891'>2891</a>
<a id='n2892' href='#n2892'>2892</a>
<a id='n2893' href='#n2893'>2893</a>
<a id='n2894' href='#n2894'>2894</a>
<a id='n2895' href='#n2895'>2895</a>
<a id='n2896' href='#n2896'>2896</a>
<a id='n2897' href='#n2897'>2897</a>
<a id='n2898' href='#n2898'>2898</a>
<a id='n2899' href='#n2899'>2899</a>
<a id='n2900' href='#n2900'>2900</a>
<a id='n2901' href='#n2901'>2901</a>
<a id='n2902' href='#n2902'>2902</a>
<a id='n2903' href='#n2903'>2903</a>
<a id='n2904' href='#n2904'>2904</a>
<a id='n2905' href='#n2905'>2905</a>
<a id='n2906' href='#n2906'>2906</a>
<a id='n2907' href='#n2907'>2907</a>
<a id='n2908' href='#n2908'>2908</a>
<a id='n2909' href='#n2909'>2909</a>
<a id='n2910' href='#n2910'>2910</a>
<a id='n2911' href='#n2911'>2911</a>
<a id='n2912' href='#n2912'>2912</a>
<a id='n2913' href='#n2913'>2913</a>
<a id='n2914' href='#n2914'>2914</a>
<a id='n2915' href='#n2915'>2915</a>
<a id='n2916' href='#n2916'>2916</a>
<a id='n2917' href='#n2917'>2917</a>
<a id='n2918' href='#n2918'>2918</a>
<a id='n2919' href='#n2919'>2919</a>
<a id='n2920' href='#n2920'>2920</a>
<a id='n2921' href='#n2921'>2921</a>
<a id='n2922' href='#n2922'>2922</a>
<a id='n2923' href='#n2923'>2923</a>
<a id='n2924' href='#n2924'>2924</a>
<a id='n2925' href='#n2925'>2925</a>
<a id='n2926' href='#n2926'>2926</a>
<a id='n2927' href='#n2927'>2927</a>
<a id='n2928' href='#n2928'>2928</a>
<a id='n2929' href='#n2929'>2929</a>
<a id='n2930' href='#n2930'>2930</a>
<a id='n2931' href='#n2931'>2931</a>
<a id='n2932' href='#n2932'>2932</a>
<a id='n2933' href='#n2933'>2933</a>
<a id='n2934' href='#n2934'>2934</a>
<a id='n2935' href='#n2935'>2935</a>
<a id='n2936' href='#n2936'>2936</a>
<a id='n2937' href='#n2937'>2937</a>
<a id='n2938' href='#n2938'>2938</a>
<a id='n2939' href='#n2939'>2939</a>
<a id='n2940' href='#n2940'>2940</a>
<a id='n2941' href='#n2941'>2941</a>
<a id='n2942' href='#n2942'>2942</a>
<a id='n2943' href='#n2943'>2943</a>
<a id='n2944' href='#n2944'>2944</a>
<a id='n2945' href='#n2945'>2945</a>
<a id='n2946' href='#n2946'>2946</a>
<a id='n2947' href='#n2947'>2947</a>
<a id='n2948' href='#n2948'>2948</a>
<a id='n2949' href='#n2949'>2949</a>
<a id='n2950' href='#n2950'>2950</a>
<a id='n2951' href='#n2951'>2951</a>
<a id='n2952' href='#n2952'>2952</a>
<a id='n2953' href='#n2953'>2953</a>
<a id='n2954' href='#n2954'>2954</a>
<a id='n2955' href='#n2955'>2955</a>
<a id='n2956' href='#n2956'>2956</a>
<a id='n2957' href='#n2957'>2957</a>
<a id='n2958' href='#n2958'>2958</a>
<a id='n2959' href='#n2959'>2959</a>
<a id='n2960' href='#n2960'>2960</a>
<a id='n2961' href='#n2961'>2961</a>
<a id='n2962' href='#n2962'>2962</a>
<a id='n2963' href='#n2963'>2963</a>
<a id='n2964' href='#n2964'>2964</a>
<a id='n2965' href='#n2965'>2965</a>
<a id='n2966' href='#n2966'>2966</a>
<a id='n2967' href='#n2967'>2967</a>
<a id='n2968' href='#n2968'>2968</a>
<a id='n2969' href='#n2969'>2969</a>
<a id='n2970' href='#n2970'>2970</a>
<a id='n2971' href='#n2971'>2971</a>
<a id='n2972' href='#n2972'>2972</a>
<a id='n2973' href='#n2973'>2973</a>
<a id='n2974' href='#n2974'>2974</a>
<a id='n2975' href='#n2975'>2975</a>
<a id='n2976' href='#n2976'>2976</a>
<a id='n2977' href='#n2977'>2977</a>
<a id='n2978' href='#n2978'>2978</a>
<a id='n2979' href='#n2979'>2979</a>
<a id='n2980' href='#n2980'>2980</a>
<a id='n2981' href='#n2981'>2981</a>
<a id='n2982' href='#n2982'>2982</a>
<a id='n2983' href='#n2983'>2983</a>
<a id='n2984' href='#n2984'>2984</a>
<a id='n2985' href='#n2985'>2985</a>
<a id='n2986' href='#n2986'>2986</a>
<a id='n2987' href='#n2987'>2987</a>
<a id='n2988' href='#n2988'>2988</a>
<a id='n2989' href='#n2989'>2989</a>
<a id='n2990' href='#n2990'>2990</a>
<a id='n2991' href='#n2991'>2991</a>
<a id='n2992' href='#n2992'>2992</a>
<a id='n2993' href='#n2993'>2993</a>
<a id='n2994' href='#n2994'>2994</a>
<a id='n2995' href='#n2995'>2995</a>
<a id='n2996' href='#n2996'>2996</a>
<a id='n2997' href='#n2997'>2997</a>
<a id='n2998' href='#n2998'>2998</a>
<a id='n2999' href='#n2999'>2999</a>
<a id='n3000' href='#n3000'>3000</a>
<a id='n3001' href='#n3001'>3001</a>
<a id='n3002' href='#n3002'>3002</a>
<a id='n3003' href='#n3003'>3003</a>
<a id='n3004' href='#n3004'>3004</a>
<a id='n3005' href='#n3005'>3005</a>
<a id='n3006' href='#n3006'>3006</a>
<a id='n3007' href='#n3007'>3007</a>
<a id='n3008' href='#n3008'>3008</a>
<a id='n3009' href='#n3009'>3009</a>
<a id='n3010' href='#n3010'>3010</a>
<a id='n3011' href='#n3011'>3011</a>
<a id='n3012' href='#n3012'>3012</a>
<a id='n3013' href='#n3013'>3013</a>
<a id='n3014' href='#n3014'>3014</a>
<a id='n3015' href='#n3015'>3015</a>
<a id='n3016' href='#n3016'>3016</a>
<a id='n3017' href='#n3017'>3017</a>
<a id='n3018' href='#n3018'>3018</a>
<a id='n3019' href='#n3019'>3019</a>
<a id='n3020' href='#n3020'>3020</a>
<a id='n3021' href='#n3021'>3021</a>
<a id='n3022' href='#n3022'>3022</a>
<a id='n3023' href='#n3023'>3023</a>
<a id='n3024' href='#n3024'>3024</a>
<a id='n3025' href='#n3025'>3025</a>
<a id='n3026' href='#n3026'>3026</a>
<a id='n3027' href='#n3027'>3027</a>
<a id='n3028' href='#n3028'>3028</a>
<a id='n3029' href='#n3029'>3029</a>
<a id='n3030' href='#n3030'>3030</a>
<a id='n3031' href='#n3031'>3031</a>
<a id='n3032' href='#n3032'>3032</a>
<a id='n3033' href='#n3033'>3033</a>
<a id='n3034' href='#n3034'>3034</a>
<a id='n3035' href='#n3035'>3035</a>
<a id='n3036' href='#n3036'>3036</a>
<a id='n3037' href='#n3037'>3037</a>
<a id='n3038' href='#n3038'>3038</a>
<a id='n3039' href='#n3039'>3039</a>
<a id='n3040' href='#n3040'>3040</a>
<a id='n3041' href='#n3041'>3041</a>
<a id='n3042' href='#n3042'>3042</a>
<a id='n3043' href='#n3043'>3043</a>
<a id='n3044' href='#n3044'>3044</a>
<a id='n3045' href='#n3045'>3045</a>
<a id='n3046' href='#n3046'>3046</a>
<a id='n3047' href='#n3047'>3047</a>
<a id='n3048' href='#n3048'>3048</a>
<a id='n3049' href='#n3049'>3049</a>
<a id='n3050' href='#n3050'>3050</a>
<a id='n3051' href='#n3051'>3051</a>
<a id='n3052' href='#n3052'>3052</a>
<a id='n3053' href='#n3053'>3053</a>
<a id='n3054' href='#n3054'>3054</a>
<a id='n3055' href='#n3055'>3055</a>
<a id='n3056' href='#n3056'>3056</a>
<a id='n3057' href='#n3057'>3057</a>
<a id='n3058' href='#n3058'>3058</a>
<a id='n3059' href='#n3059'>3059</a>
<a id='n3060' href='#n3060'>3060</a>
<a id='n3061' href='#n3061'>3061</a>
<a id='n3062' href='#n3062'>3062</a>
<a id='n3063' href='#n3063'>3063</a>
<a id='n3064' href='#n3064'>3064</a>
<a id='n3065' href='#n3065'>3065</a>
<a id='n3066' href='#n3066'>3066</a>
<a id='n3067' href='#n3067'>3067</a>
<a id='n3068' href='#n3068'>3068</a>
<a id='n3069' href='#n3069'>3069</a>
<a id='n3070' href='#n3070'>3070</a>
<a id='n3071' href='#n3071'>3071</a>
<a id='n3072' href='#n3072'>3072</a>
<a id='n3073' href='#n3073'>3073</a>
<a id='n3074' href='#n3074'>3074</a>
<a id='n3075' href='#n3075'>3075</a>
<a id='n3076' href='#n3076'>3076</a>
<a id='n3077' href='#n3077'>3077</a>
<a id='n3078' href='#n3078'>3078</a>
<a id='n3079' href='#n3079'>3079</a>
<a id='n3080' href='#n3080'>3080</a>
<a id='n3081' href='#n3081'>3081</a>
<a id='n3082' href='#n3082'>3082</a>
<a id='n3083' href='#n3083'>3083</a>
<a id='n3084' href='#n3084'>3084</a>
<a id='n3085' href='#n3085'>3085</a>
<a id='n3086' href='#n3086'>3086</a>
<a id='n3087' href='#n3087'>3087</a>
<a id='n3088' href='#n3088'>3088</a>
<a id='n3089' href='#n3089'>3089</a>
<a id='n3090' href='#n3090'>3090</a>
<a id='n3091' href='#n3091'>3091</a>
<a id='n3092' href='#n3092'>3092</a>
<a id='n3093' href='#n3093'>3093</a>
<a id='n3094' href='#n3094'>3094</a>
<a id='n3095' href='#n3095'>3095</a>
<a id='n3096' href='#n3096'>3096</a>
<a id='n3097' href='#n3097'>3097</a>
<a id='n3098' href='#n3098'>3098</a>
<a id='n3099' href='#n3099'>3099</a>
<a id='n3100' href='#n3100'>3100</a>
<a id='n3101' href='#n3101'>3101</a>
<a id='n3102' href='#n3102'>3102</a>
<a id='n3103' href='#n3103'>3103</a>
<a id='n3104' href='#n3104'>3104</a>
<a id='n3105' href='#n3105'>3105</a>
<a id='n3106' href='#n3106'>3106</a>
<a id='n3107' href='#n3107'>3107</a>
<a id='n3108' href='#n3108'>3108</a>
<a id='n3109' href='#n3109'>3109</a>
<a id='n3110' href='#n3110'>3110</a>
<a id='n3111' href='#n3111'>3111</a>
<a id='n3112' href='#n3112'>3112</a>
<a id='n3113' href='#n3113'>3113</a>
<a id='n3114' href='#n3114'>3114</a>
<a id='n3115' href='#n3115'>3115</a>
<a id='n3116' href='#n3116'>3116</a>
<a id='n3117' href='#n3117'>3117</a>
<a id='n3118' href='#n3118'>3118</a>
<a id='n3119' href='#n3119'>3119</a>
<a id='n3120' href='#n3120'>3120</a>
<a id='n3121' href='#n3121'>3121</a>
<a id='n3122' href='#n3122'>3122</a>
<a id='n3123' href='#n3123'>3123</a>
<a id='n3124' href='#n3124'>3124</a>
<a id='n3125' href='#n3125'>3125</a>
<a id='n3126' href='#n3126'>3126</a>
<a id='n3127' href='#n3127'>3127</a>
<a id='n3128' href='#n3128'>3128</a>
<a id='n3129' href='#n3129'>3129</a>
<a id='n3130' href='#n3130'>3130</a>
<a id='n3131' href='#n3131'>3131</a>
<a id='n3132' href='#n3132'>3132</a>
<a id='n3133' href='#n3133'>3133</a>
<a id='n3134' href='#n3134'>3134</a>
<a id='n3135' href='#n3135'>3135</a>
<a id='n3136' href='#n3136'>3136</a>
<a id='n3137' href='#n3137'>3137</a>
<a id='n3138' href='#n3138'>3138</a>
<a id='n3139' href='#n3139'>3139</a>
<a id='n3140' href='#n3140'>3140</a>
<a id='n3141' href='#n3141'>3141</a>
<a id='n3142' href='#n3142'>3142</a>
<a id='n3143' href='#n3143'>3143</a>
<a id='n3144' href='#n3144'>3144</a>
<a id='n3145' href='#n3145'>3145</a>
<a id='n3146' href='#n3146'>3146</a>
<a id='n3147' href='#n3147'>3147</a>
<a id='n3148' href='#n3148'>3148</a>
<a id='n3149' href='#n3149'>3149</a>
<a id='n3150' href='#n3150'>3150</a>
<a id='n3151' href='#n3151'>3151</a>
<a id='n3152' href='#n3152'>3152</a>
<a id='n3153' href='#n3153'>3153</a>
<a id='n3154' href='#n3154'>3154</a>
<a id='n3155' href='#n3155'>3155</a>
<a id='n3156' href='#n3156'>3156</a>
<a id='n3157' href='#n3157'>3157</a>
<a id='n3158' href='#n3158'>3158</a>
<a id='n3159' href='#n3159'>3159</a>
<a id='n3160' href='#n3160'>3160</a>
<a id='n3161' href='#n3161'>3161</a>
<a id='n3162' href='#n3162'>3162</a>
<a id='n3163' href='#n3163'>3163</a>
<a id='n3164' href='#n3164'>3164</a>
<a id='n3165' href='#n3165'>3165</a>
<a id='n3166' href='#n3166'>3166</a>
<a id='n3167' href='#n3167'>3167</a>
<a id='n3168' href='#n3168'>3168</a>
<a id='n3169' href='#n3169'>3169</a>
<a id='n3170' href='#n3170'>3170</a>
<a id='n3171' href='#n3171'>3171</a>
<a id='n3172' href='#n3172'>3172</a>
<a id='n3173' href='#n3173'>3173</a>
<a id='n3174' href='#n3174'>3174</a>
<a id='n3175' href='#n3175'>3175</a>
<a id='n3176' href='#n3176'>3176</a>
<a id='n3177' href='#n3177'>3177</a>
<a id='n3178' href='#n3178'>3178</a>
<a id='n3179' href='#n3179'>3179</a>
<a id='n3180' href='#n3180'>3180</a>
<a id='n3181' href='#n3181'>3181</a>
<a id='n3182' href='#n3182'>3182</a>
<a id='n3183' href='#n3183'>3183</a>
<a id='n3184' href='#n3184'>3184</a>
<a id='n3185' href='#n3185'>3185</a>
<a id='n3186' href='#n3186'>3186</a>
<a id='n3187' href='#n3187'>3187</a>
<a id='n3188' href='#n3188'>3188</a>
<a id='n3189' href='#n3189'>3189</a>
<a id='n3190' href='#n3190'>3190</a>
<a id='n3191' href='#n3191'>3191</a>
<a id='n3192' href='#n3192'>3192</a>
<a id='n3193' href='#n3193'>3193</a>
<a id='n3194' href='#n3194'>3194</a>
<a id='n3195' href='#n3195'>3195</a>
<a id='n3196' href='#n3196'>3196</a>
<a id='n3197' href='#n3197'>3197</a>
<a id='n3198' href='#n3198'>3198</a>
<a id='n3199' href='#n3199'>3199</a>
<a id='n3200' href='#n3200'>3200</a>
<a id='n3201' href='#n3201'>3201</a>
<a id='n3202' href='#n3202'>3202</a>
<a id='n3203' href='#n3203'>3203</a>
<a id='n3204' href='#n3204'>3204</a>
<a id='n3205' href='#n3205'>3205</a>
<a id='n3206' href='#n3206'>3206</a>
<a id='n3207' href='#n3207'>3207</a>
<a id='n3208' href='#n3208'>3208</a>
<a id='n3209' href='#n3209'>3209</a>
<a id='n3210' href='#n3210'>3210</a>
<a id='n3211' href='#n3211'>3211</a>
<a id='n3212' href='#n3212'>3212</a>
<a id='n3213' href='#n3213'>3213</a>
<a id='n3214' href='#n3214'>3214</a>
<a id='n3215' href='#n3215'>3215</a>
<a id='n3216' href='#n3216'>3216</a>
<a id='n3217' href='#n3217'>3217</a>
<a id='n3218' href='#n3218'>3218</a>
<a id='n3219' href='#n3219'>3219</a>
<a id='n3220' href='#n3220'>3220</a>
<a id='n3221' href='#n3221'>3221</a>
<a id='n3222' href='#n3222'>3222</a>
<a id='n3223' href='#n3223'>3223</a>
<a id='n3224' href='#n3224'>3224</a>
<a id='n3225' href='#n3225'>3225</a>
<a id='n3226' href='#n3226'>3226</a>
<a id='n3227' href='#n3227'>3227</a>
<a id='n3228' href='#n3228'>3228</a>
<a id='n3229' href='#n3229'>3229</a>
<a id='n3230' href='#n3230'>3230</a>
<a id='n3231' href='#n3231'>3231</a>
<a id='n3232' href='#n3232'>3232</a>
<a id='n3233' href='#n3233'>3233</a>
<a id='n3234' href='#n3234'>3234</a>
<a id='n3235' href='#n3235'>3235</a>
<a id='n3236' href='#n3236'>3236</a>
<a id='n3237' href='#n3237'>3237</a>
<a id='n3238' href='#n3238'>3238</a>
<a id='n3239' href='#n3239'>3239</a>
<a id='n3240' href='#n3240'>3240</a>
<a id='n3241' href='#n3241'>3241</a>
<a id='n3242' href='#n3242'>3242</a>
<a id='n3243' href='#n3243'>3243</a>
<a id='n3244' href='#n3244'>3244</a>
<a id='n3245' href='#n3245'>3245</a>
<a id='n3246' href='#n3246'>3246</a>
<a id='n3247' href='#n3247'>3247</a>
<a id='n3248' href='#n3248'>3248</a>
<a id='n3249' href='#n3249'>3249</a>
<a id='n3250' href='#n3250'>3250</a>
<a id='n3251' href='#n3251'>3251</a>
<a id='n3252' href='#n3252'>3252</a>
<a id='n3253' href='#n3253'>3253</a>
<a id='n3254' href='#n3254'>3254</a>
<a id='n3255' href='#n3255'>3255</a>
<a id='n3256' href='#n3256'>3256</a>
<a id='n3257' href='#n3257'>3257</a>
<a id='n3258' href='#n3258'>3258</a>
<a id='n3259' href='#n3259'>3259</a>
<a id='n3260' href='#n3260'>3260</a>
<a id='n3261' href='#n3261'>3261</a>
<a id='n3262' href='#n3262'>3262</a>
<a id='n3263' href='#n3263'>3263</a>
<a id='n3264' href='#n3264'>3264</a>
<a id='n3265' href='#n3265'>3265</a>
<a id='n3266' href='#n3266'>3266</a>
<a id='n3267' href='#n3267'>3267</a>
<a id='n3268' href='#n3268'>3268</a>
<a id='n3269' href='#n3269'>3269</a>
<a id='n3270' href='#n3270'>3270</a>
<a id='n3271' href='#n3271'>3271</a>
<a id='n3272' href='#n3272'>3272</a>
<a id='n3273' href='#n3273'>3273</a>
<a id='n3274' href='#n3274'>3274</a>
<a id='n3275' href='#n3275'>3275</a>
<a id='n3276' href='#n3276'>3276</a>
<a id='n3277' href='#n3277'>3277</a>
<a id='n3278' href='#n3278'>3278</a>
<a id='n3279' href='#n3279'>3279</a>
<a id='n3280' href='#n3280'>3280</a>
<a id='n3281' href='#n3281'>3281</a>
<a id='n3282' href='#n3282'>3282</a>
<a id='n3283' href='#n3283'>3283</a>
<a id='n3284' href='#n3284'>3284</a>
<a id='n3285' href='#n3285'>3285</a>
<a id='n3286' href='#n3286'>3286</a>
<a id='n3287' href='#n3287'>3287</a>
<a id='n3288' href='#n3288'>3288</a>
<a id='n3289' href='#n3289'>3289</a>
<a id='n3290' href='#n3290'>3290</a>
<a id='n3291' href='#n3291'>3291</a>
<a id='n3292' href='#n3292'>3292</a>
<a id='n3293' href='#n3293'>3293</a>
<a id='n3294' href='#n3294'>3294</a>
<a id='n3295' href='#n3295'>3295</a>
<a id='n3296' href='#n3296'>3296</a>
<a id='n3297' href='#n3297'>3297</a>
<a id='n3298' href='#n3298'>3298</a>
<a id='n3299' href='#n3299'>3299</a>
<a id='n3300' href='#n3300'>3300</a>
<a id='n3301' href='#n3301'>3301</a>
<a id='n3302' href='#n3302'>3302</a>
<a id='n3303' href='#n3303'>3303</a>
<a id='n3304' href='#n3304'>3304</a>
<a id='n3305' href='#n3305'>3305</a>
<a id='n3306' href='#n3306'>3306</a>
<a id='n3307' href='#n3307'>3307</a>
<a id='n3308' href='#n3308'>3308</a>
<a id='n3309' href='#n3309'>3309</a>
<a id='n3310' href='#n3310'>3310</a>
<a id='n3311' href='#n3311'>3311</a>
<a id='n3312' href='#n3312'>3312</a>
<a id='n3313' href='#n3313'>3313</a>
<a id='n3314' href='#n3314'>3314</a>
<a id='n3315' href='#n3315'>3315</a>
<a id='n3316' href='#n3316'>3316</a>
<a id='n3317' href='#n3317'>3317</a>
<a id='n3318' href='#n3318'>3318</a>
<a id='n3319' href='#n3319'>3319</a>
<a id='n3320' href='#n3320'>3320</a>
<a id='n3321' href='#n3321'>3321</a>
<a id='n3322' href='#n3322'>3322</a>
<a id='n3323' href='#n3323'>3323</a>
<a id='n3324' href='#n3324'>3324</a>
<a id='n3325' href='#n3325'>3325</a>
<a id='n3326' href='#n3326'>3326</a>
<a id='n3327' href='#n3327'>3327</a>
<a id='n3328' href='#n3328'>3328</a>
<a id='n3329' href='#n3329'>3329</a>
<a id='n3330' href='#n3330'>3330</a>
<a id='n3331' href='#n3331'>3331</a>
<a id='n3332' href='#n3332'>3332</a>
<a id='n3333' href='#n3333'>3333</a>
<a id='n3334' href='#n3334'>3334</a>
<a id='n3335' href='#n3335'>3335</a>
<a id='n3336' href='#n3336'>3336</a>
<a id='n3337' href='#n3337'>3337</a>
<a id='n3338' href='#n3338'>3338</a>
<a id='n3339' href='#n3339'>3339</a>
<a id='n3340' href='#n3340'>3340</a>
<a id='n3341' href='#n3341'>3341</a>
<a id='n3342' href='#n3342'>3342</a>
<a id='n3343' href='#n3343'>3343</a>
<a id='n3344' href='#n3344'>3344</a>
<a id='n3345' href='#n3345'>3345</a>
<a id='n3346' href='#n3346'>3346</a>
<a id='n3347' href='#n3347'>3347</a>
<a id='n3348' href='#n3348'>3348</a>
<a id='n3349' href='#n3349'>3349</a>
<a id='n3350' href='#n3350'>3350</a>
<a id='n3351' href='#n3351'>3351</a>
<a id='n3352' href='#n3352'>3352</a>
<a id='n3353' href='#n3353'>3353</a>
<a id='n3354' href='#n3354'>3354</a>
<a id='n3355' href='#n3355'>3355</a>
<a id='n3356' href='#n3356'>3356</a>
<a id='n3357' href='#n3357'>3357</a>
<a id='n3358' href='#n3358'>3358</a>
<a id='n3359' href='#n3359'>3359</a>
<a id='n3360' href='#n3360'>3360</a>
<a id='n3361' href='#n3361'>3361</a>
<a id='n3362' href='#n3362'>3362</a>
<a id='n3363' href='#n3363'>3363</a>
<a id='n3364' href='#n3364'>3364</a>
<a id='n3365' href='#n3365'>3365</a>
<a id='n3366' href='#n3366'>3366</a>
<a id='n3367' href='#n3367'>3367</a>
<a id='n3368' href='#n3368'>3368</a>
<a id='n3369' href='#n3369'>3369</a>
<a id='n3370' href='#n3370'>3370</a>
<a id='n3371' href='#n3371'>3371</a>
<a id='n3372' href='#n3372'>3372</a>
<a id='n3373' href='#n3373'>3373</a>
<a id='n3374' href='#n3374'>3374</a>
<a id='n3375' href='#n3375'>3375</a>
<a id='n3376' href='#n3376'>3376</a>
<a id='n3377' href='#n3377'>3377</a>
<a id='n3378' href='#n3378'>3378</a>
<a id='n3379' href='#n3379'>3379</a>
<a id='n3380' href='#n3380'>3380</a>
<a id='n3381' href='#n3381'>3381</a>
<a id='n3382' href='#n3382'>3382</a>
<a id='n3383' href='#n3383'>3383</a>
<a id='n3384' href='#n3384'>3384</a>
<a id='n3385' href='#n3385'>3385</a>
<a id='n3386' href='#n3386'>3386</a>
<a id='n3387' href='#n3387'>3387</a>
<a id='n3388' href='#n3388'>3388</a>
<a id='n3389' href='#n3389'>3389</a>
<a id='n3390' href='#n3390'>3390</a>
<a id='n3391' href='#n3391'>3391</a>
<a id='n3392' href='#n3392'>3392</a>
<a id='n3393' href='#n3393'>3393</a>
<a id='n3394' href='#n3394'>3394</a>
<a id='n3395' href='#n3395'>3395</a>
<a id='n3396' href='#n3396'>3396</a>
<a id='n3397' href='#n3397'>3397</a>
<a id='n3398' href='#n3398'>3398</a>
<a id='n3399' href='#n3399'>3399</a>
<a id='n3400' href='#n3400'>3400</a>
<a id='n3401' href='#n3401'>3401</a>
<a id='n3402' href='#n3402'>3402</a>
<a id='n3403' href='#n3403'>3403</a>
<a id='n3404' href='#n3404'>3404</a>
<a id='n3405' href='#n3405'>3405</a>
<a id='n3406' href='#n3406'>3406</a>
<a id='n3407' href='#n3407'>3407</a>
<a id='n3408' href='#n3408'>3408</a>
<a id='n3409' href='#n3409'>3409</a>
<a id='n3410' href='#n3410'>3410</a>
<a id='n3411' href='#n3411'>3411</a>
<a id='n3412' href='#n3412'>3412</a>
<a id='n3413' href='#n3413'>3413</a>
<a id='n3414' href='#n3414'>3414</a>
<a id='n3415' href='#n3415'>3415</a>
<a id='n3416' href='#n3416'>3416</a>
<a id='n3417' href='#n3417'>3417</a>
<a id='n3418' href='#n3418'>3418</a>
<a id='n3419' href='#n3419'>3419</a>
<a id='n3420' href='#n3420'>3420</a>
<a id='n3421' href='#n3421'>3421</a>
<a id='n3422' href='#n3422'>3422</a>
<a id='n3423' href='#n3423'>3423</a>
<a id='n3424' href='#n3424'>3424</a>
<a id='n3425' href='#n3425'>3425</a>
<a id='n3426' href='#n3426'>3426</a>
<a id='n3427' href='#n3427'>3427</a>
<a id='n3428' href='#n3428'>3428</a>
<a id='n3429' href='#n3429'>3429</a>
<a id='n3430' href='#n3430'>3430</a>
<a id='n3431' href='#n3431'>3431</a>
<a id='n3432' href='#n3432'>3432</a>
<a id='n3433' href='#n3433'>3433</a>
<a id='n3434' href='#n3434'>3434</a>
<a id='n3435' href='#n3435'>3435</a>
<a id='n3436' href='#n3436'>3436</a>
<a id='n3437' href='#n3437'>3437</a>
<a id='n3438' href='#n3438'>3438</a>
<a id='n3439' href='#n3439'>3439</a>
<a id='n3440' href='#n3440'>3440</a>
<a id='n3441' href='#n3441'>3441</a>
<a id='n3442' href='#n3442'>3442</a>
<a id='n3443' href='#n3443'>3443</a>
<a id='n3444' href='#n3444'>3444</a>
<a id='n3445' href='#n3445'>3445</a>
<a id='n3446' href='#n3446'>3446</a>
<a id='n3447' href='#n3447'>3447</a>
<a id='n3448' href='#n3448'>3448</a>
<a id='n3449' href='#n3449'>3449</a>
<a id='n3450' href='#n3450'>3450</a>
<a id='n3451' href='#n3451'>3451</a>
<a id='n3452' href='#n3452'>3452</a>
<a id='n3453' href='#n3453'>3453</a>
<a id='n3454' href='#n3454'>3454</a>
<a id='n3455' href='#n3455'>3455</a>
<a id='n3456' href='#n3456'>3456</a>
<a id='n3457' href='#n3457'>3457</a>
<a id='n3458' href='#n3458'>3458</a>
<a id='n3459' href='#n3459'>3459</a>
<a id='n3460' href='#n3460'>3460</a>
<a id='n3461' href='#n3461'>3461</a>
<a id='n3462' href='#n3462'>3462</a>
<a id='n3463' href='#n3463'>3463</a>
<a id='n3464' href='#n3464'>3464</a>
<a id='n3465' href='#n3465'>3465</a>
<a id='n3466' href='#n3466'>3466</a>
<a id='n3467' href='#n3467'>3467</a>
<a id='n3468' href='#n3468'>3468</a>
<a id='n3469' href='#n3469'>3469</a>
<a id='n3470' href='#n3470'>3470</a>
<a id='n3471' href='#n3471'>3471</a>
<a id='n3472' href='#n3472'>3472</a>
<a id='n3473' href='#n3473'>3473</a>
<a id='n3474' href='#n3474'>3474</a>
<a id='n3475' href='#n3475'>3475</a>
<a id='n3476' href='#n3476'>3476</a>
<a id='n3477' href='#n3477'>3477</a>
<a id='n3478' href='#n3478'>3478</a>
<a id='n3479' href='#n3479'>3479</a>
<a id='n3480' href='#n3480'>3480</a>
<a id='n3481' href='#n3481'>3481</a>
<a id='n3482' href='#n3482'>3482</a>
<a id='n3483' href='#n3483'>3483</a>
<a id='n3484' href='#n3484'>3484</a>
<a id='n3485' href='#n3485'>3485</a>
<a id='n3486' href='#n3486'>3486</a>
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<a id='n3512' href='#n3512'>3512</a>
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<a id='n3521' href='#n3521'>3521</a>
<a id='n3522' href='#n3522'>3522</a>
<a id='n3523' href='#n3523'>3523</a>
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<a id='n3528' href='#n3528'>3528</a>
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<a id='n3530' href='#n3530'>3530</a>
<a id='n3531' href='#n3531'>3531</a>
<a id='n3532' href='#n3532'>3532</a>
<a id='n3533' href='#n3533'>3533</a>
<a id='n3534' href='#n3534'>3534</a>
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<a id='n3538' href='#n3538'>3538</a>
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<a id='n3560' href='#n3560'>3560</a>
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<a id='n3562' href='#n3562'>3562</a>
<a id='n3563' href='#n3563'>3563</a>
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<a id='n3568' href='#n3568'>3568</a>
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<a id='n3570' href='#n3570'>3570</a>
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<a id='n3572' href='#n3572'>3572</a>
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<a id='n3577' href='#n3577'>3577</a>
<a id='n3578' href='#n3578'>3578</a>
<a id='n3579' href='#n3579'>3579</a>
<a id='n3580' href='#n3580'>3580</a>
<a id='n3581' href='#n3581'>3581</a>
<a id='n3582' href='#n3582'>3582</a>
<a id='n3583' href='#n3583'>3583</a>
<a id='n3584' href='#n3584'>3584</a>
<a id='n3585' href='#n3585'>3585</a>
<a id='n3586' href='#n3586'>3586</a>
<a id='n3587' href='#n3587'>3587</a>
<a id='n3588' href='#n3588'>3588</a>
<a id='n3589' href='#n3589'>3589</a>
<a id='n3590' href='#n3590'>3590</a>
<a id='n3591' href='#n3591'>3591</a>
<a id='n3592' href='#n3592'>3592</a>
<a id='n3593' href='#n3593'>3593</a>
<a id='n3594' href='#n3594'>3594</a>
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<a id='n3596' href='#n3596'>3596</a>
<a id='n3597' href='#n3597'>3597</a>
<a id='n3598' href='#n3598'>3598</a>
<a id='n3599' href='#n3599'>3599</a>
<a id='n3600' href='#n3600'>3600</a>
<a id='n3601' href='#n3601'>3601</a>
<a id='n3602' href='#n3602'>3602</a>
<a id='n3603' href='#n3603'>3603</a>
<a id='n3604' href='#n3604'>3604</a>
<a id='n3605' href='#n3605'>3605</a>
<a id='n3606' href='#n3606'>3606</a>
<a id='n3607' href='#n3607'>3607</a>
<a id='n3608' href='#n3608'>3608</a>
<a id='n3609' href='#n3609'>3609</a>
<a id='n3610' href='#n3610'>3610</a>
<a id='n3611' href='#n3611'>3611</a>
<a id='n3612' href='#n3612'>3612</a>
<a id='n3613' href='#n3613'>3613</a>
<a id='n3614' href='#n3614'>3614</a>
<a id='n3615' href='#n3615'>3615</a>
<a id='n3616' href='#n3616'>3616</a>
<a id='n3617' href='#n3617'>3617</a>
<a id='n3618' href='#n3618'>3618</a>
<a id='n3619' href='#n3619'>3619</a>
<a id='n3620' href='#n3620'>3620</a>
<a id='n3621' href='#n3621'>3621</a>
<a id='n3622' href='#n3622'>3622</a>
<a id='n3623' href='#n3623'>3623</a>
<a id='n3624' href='#n3624'>3624</a>
<a id='n3625' href='#n3625'>3625</a>
<a id='n3626' href='#n3626'>3626</a>
<a id='n3627' href='#n3627'>3627</a>
<a id='n3628' href='#n3628'>3628</a>
<a id='n3629' href='#n3629'>3629</a>
<a id='n3630' href='#n3630'>3630</a>
<a id='n3631' href='#n3631'>3631</a>
<a id='n3632' href='#n3632'>3632</a>
<a id='n3633' href='#n3633'>3633</a>
<a id='n3634' href='#n3634'>3634</a>
<a id='n3635' href='#n3635'>3635</a>
<a id='n3636' href='#n3636'>3636</a>
<a id='n3637' href='#n3637'>3637</a>
<a id='n3638' href='#n3638'>3638</a>
<a id='n3639' href='#n3639'>3639</a>
<a id='n3640' href='#n3640'>3640</a>
<a id='n3641' href='#n3641'>3641</a>
<a id='n3642' href='#n3642'>3642</a>
<a id='n3643' href='#n3643'>3643</a>
<a id='n3644' href='#n3644'>3644</a>
<a id='n3645' href='#n3645'>3645</a>
<a id='n3646' href='#n3646'>3646</a>
<a id='n3647' href='#n3647'>3647</a>
<a id='n3648' href='#n3648'>3648</a>
<a id='n3649' href='#n3649'>3649</a>
<a id='n3650' href='#n3650'>3650</a>
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<a id='n3652' href='#n3652'>3652</a>
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<a id='n3663' href='#n3663'>3663</a>
<a id='n3664' href='#n3664'>3664</a>
<a id='n3665' href='#n3665'>3665</a>
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<a id='n3667' href='#n3667'>3667</a>
<a id='n3668' href='#n3668'>3668</a>
<a id='n3669' href='#n3669'>3669</a>
<a id='n3670' href='#n3670'>3670</a>
<a id='n3671' href='#n3671'>3671</a>
<a id='n3672' href='#n3672'>3672</a>
<a id='n3673' href='#n3673'>3673</a>
<a id='n3674' href='#n3674'>3674</a>
<a id='n3675' href='#n3675'>3675</a>
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<a id='n3677' href='#n3677'>3677</a>
<a id='n3678' href='#n3678'>3678</a>
<a id='n3679' href='#n3679'>3679</a>
<a id='n3680' href='#n3680'>3680</a>
<a id='n3681' href='#n3681'>3681</a>
<a id='n3682' href='#n3682'>3682</a>
<a id='n3683' href='#n3683'>3683</a>
<a id='n3684' href='#n3684'>3684</a>
<a id='n3685' href='#n3685'>3685</a>
<a id='n3686' href='#n3686'>3686</a>
<a id='n3687' href='#n3687'>3687</a>
<a id='n3688' href='#n3688'>3688</a>
<a id='n3689' href='#n3689'>3689</a>
<a id='n3690' href='#n3690'>3690</a>
<a id='n3691' href='#n3691'>3691</a>
<a id='n3692' href='#n3692'>3692</a>
<a id='n3693' href='#n3693'>3693</a>
<a id='n3694' href='#n3694'>3694</a>
<a id='n3695' href='#n3695'>3695</a>
<a id='n3696' href='#n3696'>3696</a>
<a id='n3697' href='#n3697'>3697</a>
<a id='n3698' href='#n3698'>3698</a>
<a id='n3699' href='#n3699'>3699</a>
<a id='n3700' href='#n3700'>3700</a>
<a id='n3701' href='#n3701'>3701</a>
<a id='n3702' href='#n3702'>3702</a>
<a id='n3703' href='#n3703'>3703</a>
<a id='n3704' href='#n3704'>3704</a>
<a id='n3705' href='#n3705'>3705</a>
<a id='n3706' href='#n3706'>3706</a>
<a id='n3707' href='#n3707'>3707</a>
<a id='n3708' href='#n3708'>3708</a>
<a id='n3709' href='#n3709'>3709</a>
<a id='n3710' href='#n3710'>3710</a>
<a id='n3711' href='#n3711'>3711</a>
<a id='n3712' href='#n3712'>3712</a>
<a id='n3713' href='#n3713'>3713</a>
<a id='n3714' href='#n3714'>3714</a>
<a id='n3715' href='#n3715'>3715</a>
<a id='n3716' href='#n3716'>3716</a>
<a id='n3717' href='#n3717'>3717</a>
<a id='n3718' href='#n3718'>3718</a>
<a id='n3719' href='#n3719'>3719</a>
<a id='n3720' href='#n3720'>3720</a>
<a id='n3721' href='#n3721'>3721</a>
<a id='n3722' href='#n3722'>3722</a>
<a id='n3723' href='#n3723'>3723</a>
<a id='n3724' href='#n3724'>3724</a>
<a id='n3725' href='#n3725'>3725</a>
<a id='n3726' href='#n3726'>3726</a>
<a id='n3727' href='#n3727'>3727</a>
<a id='n3728' href='#n3728'>3728</a>
<a id='n3729' href='#n3729'>3729</a>
<a id='n3730' href='#n3730'>3730</a>
<a id='n3731' href='#n3731'>3731</a>
<a id='n3732' href='#n3732'>3732</a>
<a id='n3733' href='#n3733'>3733</a>
<a id='n3734' href='#n3734'>3734</a>
<a id='n3735' href='#n3735'>3735</a>
<a id='n3736' href='#n3736'>3736</a>
<a id='n3737' href='#n3737'>3737</a>
<a id='n3738' href='#n3738'>3738</a>
<a id='n3739' href='#n3739'>3739</a>
<a id='n3740' href='#n3740'>3740</a>
<a id='n3741' href='#n3741'>3741</a>
<a id='n3742' href='#n3742'>3742</a>
<a id='n3743' href='#n3743'>3743</a>
<a id='n3744' href='#n3744'>3744</a>
<a id='n3745' href='#n3745'>3745</a>
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<a id='n3747' href='#n3747'>3747</a>
<a id='n3748' href='#n3748'>3748</a>
<a id='n3749' href='#n3749'>3749</a>
<a id='n3750' href='#n3750'>3750</a>
<a id='n3751' href='#n3751'>3751</a>
<a id='n3752' href='#n3752'>3752</a>
<a id='n3753' href='#n3753'>3753</a>
<a id='n3754' href='#n3754'>3754</a>
<a id='n3755' href='#n3755'>3755</a>
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<a id='n3757' href='#n3757'>3757</a>
<a id='n3758' href='#n3758'>3758</a>
<a id='n3759' href='#n3759'>3759</a>
<a id='n3760' href='#n3760'>3760</a>
<a id='n3761' href='#n3761'>3761</a>
<a id='n3762' href='#n3762'>3762</a>
<a id='n3763' href='#n3763'>3763</a>
<a id='n3764' href='#n3764'>3764</a>
<a id='n3765' href='#n3765'>3765</a>
<a id='n3766' href='#n3766'>3766</a>
<a id='n3767' href='#n3767'>3767</a>
<a id='n3768' href='#n3768'>3768</a>
<a id='n3769' href='#n3769'>3769</a>
<a id='n3770' href='#n3770'>3770</a>
<a id='n3771' href='#n3771'>3771</a>
<a id='n3772' href='#n3772'>3772</a>
<a id='n3773' href='#n3773'>3773</a>
<a id='n3774' href='#n3774'>3774</a>
<a id='n3775' href='#n3775'>3775</a>
<a id='n3776' href='#n3776'>3776</a>
<a id='n3777' href='#n3777'>3777</a>
<a id='n3778' href='#n3778'>3778</a>
<a id='n3779' href='#n3779'>3779</a>
<a id='n3780' href='#n3780'>3780</a>
<a id='n3781' href='#n3781'>3781</a>
<a id='n3782' href='#n3782'>3782</a>
<a id='n3783' href='#n3783'>3783</a>
<a id='n3784' href='#n3784'>3784</a>
<a id='n3785' href='#n3785'>3785</a>
<a id='n3786' href='#n3786'>3786</a>
<a id='n3787' href='#n3787'>3787</a>
<a id='n3788' href='#n3788'>3788</a>
<a id='n3789' href='#n3789'>3789</a>
<a id='n3790' href='#n3790'>3790</a>
<a id='n3791' href='#n3791'>3791</a>
<a id='n3792' href='#n3792'>3792</a>
<a id='n3793' href='#n3793'>3793</a>
<a id='n3794' href='#n3794'>3794</a>
<a id='n3795' href='#n3795'>3795</a>
<a id='n3796' href='#n3796'>3796</a>
<a id='n3797' href='#n3797'>3797</a>
<a id='n3798' href='#n3798'>3798</a>
<a id='n3799' href='#n3799'>3799</a>
<a id='n3800' href='#n3800'>3800</a>
<a id='n3801' href='#n3801'>3801</a>
<a id='n3802' href='#n3802'>3802</a>
<a id='n3803' href='#n3803'>3803</a>
<a id='n3804' href='#n3804'>3804</a>
<a id='n3805' href='#n3805'>3805</a>
<a id='n3806' href='#n3806'>3806</a>
<a id='n3807' href='#n3807'>3807</a>
<a id='n3808' href='#n3808'>3808</a>
<a id='n3809' href='#n3809'>3809</a>
<a id='n3810' href='#n3810'>3810</a>
<a id='n3811' href='#n3811'>3811</a>
<a id='n3812' href='#n3812'>3812</a>
<a id='n3813' href='#n3813'>3813</a>
<a id='n3814' href='#n3814'>3814</a>
<a id='n3815' href='#n3815'>3815</a>
<a id='n3816' href='#n3816'>3816</a>
<a id='n3817' href='#n3817'>3817</a>
<a id='n3818' href='#n3818'>3818</a>
<a id='n3819' href='#n3819'>3819</a>
<a id='n3820' href='#n3820'>3820</a>
<a id='n3821' href='#n3821'>3821</a>
<a id='n3822' href='#n3822'>3822</a>
<a id='n3823' href='#n3823'>3823</a>
<a id='n3824' href='#n3824'>3824</a>
<a id='n3825' href='#n3825'>3825</a>
<a id='n3826' href='#n3826'>3826</a>
<a id='n3827' href='#n3827'>3827</a>
<a id='n3828' href='#n3828'>3828</a>
<a id='n3829' href='#n3829'>3829</a>
<a id='n3830' href='#n3830'>3830</a>
<a id='n3831' href='#n3831'>3831</a>
<a id='n3832' href='#n3832'>3832</a>
<a id='n3833' href='#n3833'>3833</a>
<a id='n3834' href='#n3834'>3834</a>
<a id='n3835' href='#n3835'>3835</a>
<a id='n3836' href='#n3836'>3836</a>
<a id='n3837' href='#n3837'>3837</a>
<a id='n3838' href='#n3838'>3838</a>
<a id='n3839' href='#n3839'>3839</a>
<a id='n3840' href='#n3840'>3840</a>
<a id='n3841' href='#n3841'>3841</a>
<a id='n3842' href='#n3842'>3842</a>
<a id='n3843' href='#n3843'>3843</a>
<a id='n3844' href='#n3844'>3844</a>
<a id='n3845' href='#n3845'>3845</a>
<a id='n3846' href='#n3846'>3846</a>
<a id='n3847' href='#n3847'>3847</a>
<a id='n3848' href='#n3848'>3848</a>
<a id='n3849' href='#n3849'>3849</a>
<a id='n3850' href='#n3850'>3850</a>
<a id='n3851' href='#n3851'>3851</a>
<a id='n3852' href='#n3852'>3852</a>
<a id='n3853' href='#n3853'>3853</a>
<a id='n3854' href='#n3854'>3854</a>
<a id='n3855' href='#n3855'>3855</a>
<a id='n3856' href='#n3856'>3856</a>
<a id='n3857' href='#n3857'>3857</a>
<a id='n3858' href='#n3858'>3858</a>
<a id='n3859' href='#n3859'>3859</a>
<a id='n3860' href='#n3860'>3860</a>
<a id='n3861' href='#n3861'>3861</a>
<a id='n3862' href='#n3862'>3862</a>
<a id='n3863' href='#n3863'>3863</a>
<a id='n3864' href='#n3864'>3864</a>
<a id='n3865' href='#n3865'>3865</a>
<a id='n3866' href='#n3866'>3866</a>
<a id='n3867' href='#n3867'>3867</a>
<a id='n3868' href='#n3868'>3868</a>
<a id='n3869' href='#n3869'>3869</a>
<a id='n3870' href='#n3870'>3870</a>
<a id='n3871' href='#n3871'>3871</a>
<a id='n3872' href='#n3872'>3872</a>
<a id='n3873' href='#n3873'>3873</a>
<a id='n3874' href='#n3874'>3874</a>
<a id='n3875' href='#n3875'>3875</a>
<a id='n3876' href='#n3876'>3876</a>
<a id='n3877' href='#n3877'>3877</a>
<a id='n3878' href='#n3878'>3878</a>
<a id='n3879' href='#n3879'>3879</a>
<a id='n3880' href='#n3880'>3880</a>
<a id='n3881' href='#n3881'>3881</a>
<a id='n3882' href='#n3882'>3882</a>
<a id='n3883' href='#n3883'>3883</a>
<a id='n3884' href='#n3884'>3884</a>
<a id='n3885' href='#n3885'>3885</a>
<a id='n3886' href='#n3886'>3886</a>
<a id='n3887' href='#n3887'>3887</a>
<a id='n3888' href='#n3888'>3888</a>
<a id='n3889' href='#n3889'>3889</a>
<a id='n3890' href='#n3890'>3890</a>
<a id='n3891' href='#n3891'>3891</a>
<a id='n3892' href='#n3892'>3892</a>
<a id='n3893' href='#n3893'>3893</a>
<a id='n3894' href='#n3894'>3894</a>
<a id='n3895' href='#n3895'>3895</a>
<a id='n3896' href='#n3896'>3896</a>
<a id='n3897' href='#n3897'>3897</a>
<a id='n3898' href='#n3898'>3898</a>
<a id='n3899' href='#n3899'>3899</a>
<a id='n3900' href='#n3900'>3900</a>
<a id='n3901' href='#n3901'>3901</a>
<a id='n3902' href='#n3902'>3902</a>
<a id='n3903' href='#n3903'>3903</a>
<a id='n3904' href='#n3904'>3904</a>
<a id='n3905' href='#n3905'>3905</a>
<a id='n3906' href='#n3906'>3906</a>
<a id='n3907' href='#n3907'>3907</a>
<a id='n3908' href='#n3908'>3908</a>
<a id='n3909' href='#n3909'>3909</a>
<a id='n3910' href='#n3910'>3910</a>
<a id='n3911' href='#n3911'>3911</a>
<a id='n3912' href='#n3912'>3912</a>
<a id='n3913' href='#n3913'>3913</a>
<a id='n3914' href='#n3914'>3914</a>
<a id='n3915' href='#n3915'>3915</a>
<a id='n3916' href='#n3916'>3916</a>
<a id='n3917' href='#n3917'>3917</a>
<a id='n3918' href='#n3918'>3918</a>
<a id='n3919' href='#n3919'>3919</a>
<a id='n3920' href='#n3920'>3920</a>
<a id='n3921' href='#n3921'>3921</a>
<a id='n3922' href='#n3922'>3922</a>
<a id='n3923' href='#n3923'>3923</a>
<a id='n3924' href='#n3924'>3924</a>
<a id='n3925' href='#n3925'>3925</a>
<a id='n3926' href='#n3926'>3926</a>
<a id='n3927' href='#n3927'>3927</a>
<a id='n3928' href='#n3928'>3928</a>
<a id='n3929' href='#n3929'>3929</a>
<a id='n3930' href='#n3930'>3930</a>
<a id='n3931' href='#n3931'>3931</a>
<a id='n3932' href='#n3932'>3932</a>
<a id='n3933' href='#n3933'>3933</a>
<a id='n3934' href='#n3934'>3934</a>
<a id='n3935' href='#n3935'>3935</a>
<a id='n3936' href='#n3936'>3936</a>
<a id='n3937' href='#n3937'>3937</a>
<a id='n3938' href='#n3938'>3938</a>
<a id='n3939' href='#n3939'>3939</a>
<a id='n3940' href='#n3940'>3940</a>
<a id='n3941' href='#n3941'>3941</a>
<a id='n3942' href='#n3942'>3942</a>
<a id='n3943' href='#n3943'>3943</a>
<a id='n3944' href='#n3944'>3944</a>
<a id='n3945' href='#n3945'>3945</a>
<a id='n3946' href='#n3946'>3946</a>
<a id='n3947' href='#n3947'>3947</a>
<a id='n3948' href='#n3948'>3948</a>
<a id='n3949' href='#n3949'>3949</a>
<a id='n3950' href='#n3950'>3950</a>
<a id='n3951' href='#n3951'>3951</a>
<a id='n3952' href='#n3952'>3952</a>
<a id='n3953' href='#n3953'>3953</a>
<a id='n3954' href='#n3954'>3954</a>
<a id='n3955' href='#n3955'>3955</a>
<a id='n3956' href='#n3956'>3956</a>
<a id='n3957' href='#n3957'>3957</a>
<a id='n3958' href='#n3958'>3958</a>
<a id='n3959' href='#n3959'>3959</a>
<a id='n3960' href='#n3960'>3960</a>
<a id='n3961' href='#n3961'>3961</a>
<a id='n3962' href='#n3962'>3962</a>
<a id='n3963' href='#n3963'>3963</a>
<a id='n3964' href='#n3964'>3964</a>
<a id='n3965' href='#n3965'>3965</a>
<a id='n3966' href='#n3966'>3966</a>
<a id='n3967' href='#n3967'>3967</a>
<a id='n3968' href='#n3968'>3968</a>
<a id='n3969' href='#n3969'>3969</a>
<a id='n3970' href='#n3970'>3970</a>
<a id='n3971' href='#n3971'>3971</a>
<a id='n3972' href='#n3972'>3972</a>
<a id='n3973' href='#n3973'>3973</a>
<a id='n3974' href='#n3974'>3974</a>
<a id='n3975' href='#n3975'>3975</a>
<a id='n3976' href='#n3976'>3976</a>
<a id='n3977' href='#n3977'>3977</a>
<a id='n3978' href='#n3978'>3978</a>
<a id='n3979' href='#n3979'>3979</a>
<a id='n3980' href='#n3980'>3980</a>
<a id='n3981' href='#n3981'>3981</a>
<a id='n3982' href='#n3982'>3982</a>
<a id='n3983' href='#n3983'>3983</a>
<a id='n3984' href='#n3984'>3984</a>
<a id='n3985' href='#n3985'>3985</a>
<a id='n3986' href='#n3986'>3986</a>
<a id='n3987' href='#n3987'>3987</a>
<a id='n3988' href='#n3988'>3988</a>
<a id='n3989' href='#n3989'>3989</a>
<a id='n3990' href='#n3990'>3990</a>
<a id='n3991' href='#n3991'>3991</a>
<a id='n3992' href='#n3992'>3992</a>
<a id='n3993' href='#n3993'>3993</a>
<a id='n3994' href='#n3994'>3994</a>
<a id='n3995' href='#n3995'>3995</a>
<a id='n3996' href='#n3996'>3996</a>
<a id='n3997' href='#n3997'>3997</a>
<a id='n3998' href='#n3998'>3998</a>
<a id='n3999' href='#n3999'>3999</a>
<a id='n4000' href='#n4000'>4000</a>
<a id='n4001' href='#n4001'>4001</a>
<a id='n4002' href='#n4002'>4002</a>
<a id='n4003' href='#n4003'>4003</a>
<a id='n4004' href='#n4004'>4004</a>
<a id='n4005' href='#n4005'>4005</a>
<a id='n4006' href='#n4006'>4006</a>
<a id='n4007' href='#n4007'>4007</a>
<a id='n4008' href='#n4008'>4008</a>
<a id='n4009' href='#n4009'>4009</a>
<a id='n4010' href='#n4010'>4010</a>
<a id='n4011' href='#n4011'>4011</a>
<a id='n4012' href='#n4012'>4012</a>
<a id='n4013' href='#n4013'>4013</a>
<a id='n4014' href='#n4014'>4014</a>
<a id='n4015' href='#n4015'>4015</a>
<a id='n4016' href='#n4016'>4016</a>
<a id='n4017' href='#n4017'>4017</a>
<a id='n4018' href='#n4018'>4018</a>
<a id='n4019' href='#n4019'>4019</a>
<a id='n4020' href='#n4020'>4020</a>
<a id='n4021' href='#n4021'>4021</a>
<a id='n4022' href='#n4022'>4022</a>
<a id='n4023' href='#n4023'>4023</a>
<a id='n4024' href='#n4024'>4024</a>
<a id='n4025' href='#n4025'>4025</a>
<a id='n4026' href='#n4026'>4026</a>
<a id='n4027' href='#n4027'>4027</a>
<a id='n4028' href='#n4028'>4028</a>
<a id='n4029' href='#n4029'>4029</a>
<a id='n4030' href='#n4030'>4030</a>
<a id='n4031' href='#n4031'>4031</a>
<a id='n4032' href='#n4032'>4032</a>
<a id='n4033' href='#n4033'>4033</a>
<a id='n4034' href='#n4034'>4034</a>
<a id='n4035' href='#n4035'>4035</a>
<a id='n4036' href='#n4036'>4036</a>
<a id='n4037' href='#n4037'>4037</a>
<a id='n4038' href='#n4038'>4038</a>
<a id='n4039' href='#n4039'>4039</a>
<a id='n4040' href='#n4040'>4040</a>
<a id='n4041' href='#n4041'>4041</a>
<a id='n4042' href='#n4042'>4042</a>
<a id='n4043' href='#n4043'>4043</a>
<a id='n4044' href='#n4044'>4044</a>
<a id='n4045' href='#n4045'>4045</a>
<a id='n4046' href='#n4046'>4046</a>
<a id='n4047' href='#n4047'>4047</a>
<a id='n4048' href='#n4048'>4048</a>
<a id='n4049' href='#n4049'>4049</a>
<a id='n4050' href='#n4050'>4050</a>
<a id='n4051' href='#n4051'>4051</a>
<a id='n4052' href='#n4052'>4052</a>
<a id='n4053' href='#n4053'>4053</a>
<a id='n4054' href='#n4054'>4054</a>
<a id='n4055' href='#n4055'>4055</a>
<a id='n4056' href='#n4056'>4056</a>
<a id='n4057' href='#n4057'>4057</a>
<a id='n4058' href='#n4058'>4058</a>
<a id='n4059' href='#n4059'>4059</a>
<a id='n4060' href='#n4060'>4060</a>
<a id='n4061' href='#n4061'>4061</a>
<a id='n4062' href='#n4062'>4062</a>
<a id='n4063' href='#n4063'>4063</a>
<a id='n4064' href='#n4064'>4064</a>
<a id='n4065' href='#n4065'>4065</a>
<a id='n4066' href='#n4066'>4066</a>
<a id='n4067' href='#n4067'>4067</a>
<a id='n4068' href='#n4068'>4068</a>
<a id='n4069' href='#n4069'>4069</a>
<a id='n4070' href='#n4070'>4070</a>
<a id='n4071' href='#n4071'>4071</a>
<a id='n4072' href='#n4072'>4072</a>
<a id='n4073' href='#n4073'>4073</a>
<a id='n4074' href='#n4074'>4074</a>
<a id='n4075' href='#n4075'>4075</a>
<a id='n4076' href='#n4076'>4076</a>
<a id='n4077' href='#n4077'>4077</a>
<a id='n4078' href='#n4078'>4078</a>
<a id='n4079' href='#n4079'>4079</a>
<a id='n4080' href='#n4080'>4080</a>
<a id='n4081' href='#n4081'>4081</a>
<a id='n4082' href='#n4082'>4082</a>
<a id='n4083' href='#n4083'>4083</a>
<a id='n4084' href='#n4084'>4084</a>
<a id='n4085' href='#n4085'>4085</a>
<a id='n4086' href='#n4086'>4086</a>
<a id='n4087' href='#n4087'>4087</a>
<a id='n4088' href='#n4088'>4088</a>
<a id='n4089' href='#n4089'>4089</a>
<a id='n4090' href='#n4090'>4090</a>
<a id='n4091' href='#n4091'>4091</a>
<a id='n4092' href='#n4092'>4092</a>
<a id='n4093' href='#n4093'>4093</a>
<a id='n4094' href='#n4094'>4094</a>
<a id='n4095' href='#n4095'>4095</a>
<a id='n4096' href='#n4096'>4096</a>
<a id='n4097' href='#n4097'>4097</a>
<a id='n4098' href='#n4098'>4098</a>
<a id='n4099' href='#n4099'>4099</a>
<a id='n4100' href='#n4100'>4100</a>
<a id='n4101' href='#n4101'>4101</a>
<a id='n4102' href='#n4102'>4102</a>
<a id='n4103' href='#n4103'>4103</a>
<a id='n4104' href='#n4104'>4104</a>
<a id='n4105' href='#n4105'>4105</a>
<a id='n4106' href='#n4106'>4106</a>
<a id='n4107' href='#n4107'>4107</a>
<a id='n4108' href='#n4108'>4108</a>
<a id='n4109' href='#n4109'>4109</a>
<a id='n4110' href='#n4110'>4110</a>
<a id='n4111' href='#n4111'>4111</a>
<a id='n4112' href='#n4112'>4112</a>
<a id='n4113' href='#n4113'>4113</a>
<a id='n4114' href='#n4114'>4114</a>
<a id='n4115' href='#n4115'>4115</a>
<a id='n4116' href='#n4116'>4116</a>
<a id='n4117' href='#n4117'>4117</a>
<a id='n4118' href='#n4118'>4118</a>
<a id='n4119' href='#n4119'>4119</a>
<a id='n4120' href='#n4120'>4120</a>
<a id='n4121' href='#n4121'>4121</a>
<a id='n4122' href='#n4122'>4122</a>
<a id='n4123' href='#n4123'>4123</a>
<a id='n4124' href='#n4124'>4124</a>
<a id='n4125' href='#n4125'>4125</a>
<a id='n4126' href='#n4126'>4126</a>
<a id='n4127' href='#n4127'>4127</a>
<a id='n4128' href='#n4128'>4128</a>
<a id='n4129' href='#n4129'>4129</a>
<a id='n4130' href='#n4130'>4130</a>
<a id='n4131' href='#n4131'>4131</a>
<a id='n4132' href='#n4132'>4132</a>
<a id='n4133' href='#n4133'>4133</a>
<a id='n4134' href='#n4134'>4134</a>
<a id='n4135' href='#n4135'>4135</a>
<a id='n4136' href='#n4136'>4136</a>
<a id='n4137' href='#n4137'>4137</a>
<a id='n4138' href='#n4138'>4138</a>
<a id='n4139' href='#n4139'>4139</a>
<a id='n4140' href='#n4140'>4140</a>
<a id='n4141' href='#n4141'>4141</a>
<a id='n4142' href='#n4142'>4142</a>
<a id='n4143' href='#n4143'>4143</a>
<a id='n4144' href='#n4144'>4144</a>
<a id='n4145' href='#n4145'>4145</a>
<a id='n4146' href='#n4146'>4146</a>
<a id='n4147' href='#n4147'>4147</a>
<a id='n4148' href='#n4148'>4148</a>
<a id='n4149' href='#n4149'>4149</a>
<a id='n4150' href='#n4150'>4150</a>
<a id='n4151' href='#n4151'>4151</a>
<a id='n4152' href='#n4152'>4152</a>
<a id='n4153' href='#n4153'>4153</a>
<a id='n4154' href='#n4154'>4154</a>
<a id='n4155' href='#n4155'>4155</a>
<a id='n4156' href='#n4156'>4156</a>
<a id='n4157' href='#n4157'>4157</a>
<a id='n4158' href='#n4158'>4158</a>
<a id='n4159' href='#n4159'>4159</a>
<a id='n4160' href='#n4160'>4160</a>
<a id='n4161' href='#n4161'>4161</a>
<a id='n4162' href='#n4162'>4162</a>
<a id='n4163' href='#n4163'>4163</a>
<a id='n4164' href='#n4164'>4164</a>
<a id='n4165' href='#n4165'>4165</a>
<a id='n4166' href='#n4166'>4166</a>
<a id='n4167' href='#n4167'>4167</a>
<a id='n4168' href='#n4168'>4168</a>
<a id='n4169' href='#n4169'>4169</a>
<a id='n4170' href='#n4170'>4170</a>
<a id='n4171' href='#n4171'>4171</a>
<a id='n4172' href='#n4172'>4172</a>
<a id='n4173' href='#n4173'>4173</a>
<a id='n4174' href='#n4174'>4174</a>
<a id='n4175' href='#n4175'>4175</a>
<a id='n4176' href='#n4176'>4176</a>
<a id='n4177' href='#n4177'>4177</a>
<a id='n4178' href='#n4178'>4178</a>
<a id='n4179' href='#n4179'>4179</a>
<a id='n4180' href='#n4180'>4180</a>
<a id='n4181' href='#n4181'>4181</a>
<a id='n4182' href='#n4182'>4182</a>
<a id='n4183' href='#n4183'>4183</a>
<a id='n4184' href='#n4184'>4184</a>
<a id='n4185' href='#n4185'>4185</a>
<a id='n4186' href='#n4186'>4186</a>
<a id='n4187' href='#n4187'>4187</a>
<a id='n4188' href='#n4188'>4188</a>
<a id='n4189' href='#n4189'>4189</a>
<a id='n4190' href='#n4190'>4190</a>
<a id='n4191' href='#n4191'>4191</a>
<a id='n4192' href='#n4192'>4192</a>
<a id='n4193' href='#n4193'>4193</a>
<a id='n4194' href='#n4194'>4194</a>
<a id='n4195' href='#n4195'>4195</a>
<a id='n4196' href='#n4196'>4196</a>
<a id='n4197' href='#n4197'>4197</a>
<a id='n4198' href='#n4198'>4198</a>
<a id='n4199' href='#n4199'>4199</a>
<a id='n4200' href='#n4200'>4200</a>
<a id='n4201' href='#n4201'>4201</a>
<a id='n4202' href='#n4202'>4202</a>
<a id='n4203' href='#n4203'>4203</a>
<a id='n4204' href='#n4204'>4204</a>
<a id='n4205' href='#n4205'>4205</a>
<a id='n4206' href='#n4206'>4206</a>
<a id='n4207' href='#n4207'>4207</a>
<a id='n4208' href='#n4208'>4208</a>
<a id='n4209' href='#n4209'>4209</a>
<a id='n4210' href='#n4210'>4210</a>
<a id='n4211' href='#n4211'>4211</a>
<a id='n4212' href='#n4212'>4212</a>
<a id='n4213' href='#n4213'>4213</a>
<a id='n4214' href='#n4214'>4214</a>
<a id='n4215' href='#n4215'>4215</a>
<a id='n4216' href='#n4216'>4216</a>
<a id='n4217' href='#n4217'>4217</a>
<a id='n4218' href='#n4218'>4218</a>
<a id='n4219' href='#n4219'>4219</a>
<a id='n4220' href='#n4220'>4220</a>
<a id='n4221' href='#n4221'>4221</a>
<a id='n4222' href='#n4222'>4222</a>
<a id='n4223' href='#n4223'>4223</a>
<a id='n4224' href='#n4224'>4224</a>
<a id='n4225' href='#n4225'>4225</a>
<a id='n4226' href='#n4226'>4226</a>
<a id='n4227' href='#n4227'>4227</a>
<a id='n4228' href='#n4228'>4228</a>
<a id='n4229' href='#n4229'>4229</a>
<a id='n4230' href='#n4230'>4230</a>
<a id='n4231' href='#n4231'>4231</a>
<a id='n4232' href='#n4232'>4232</a>
<a id='n4233' href='#n4233'>4233</a>
<a id='n4234' href='#n4234'>4234</a>
<a id='n4235' href='#n4235'>4235</a>
<a id='n4236' href='#n4236'>4236</a>
<a id='n4237' href='#n4237'>4237</a>
<a id='n4238' href='#n4238'>4238</a>
<a id='n4239' href='#n4239'>4239</a>
<a id='n4240' href='#n4240'>4240</a>
<a id='n4241' href='#n4241'>4241</a>
<a id='n4242' href='#n4242'>4242</a>
<a id='n4243' href='#n4243'>4243</a>
<a id='n4244' href='#n4244'>4244</a>
<a id='n4245' href='#n4245'>4245</a>
<a id='n4246' href='#n4246'>4246</a>
<a id='n4247' href='#n4247'>4247</a>
<a id='n4248' href='#n4248'>4248</a>
<a id='n4249' href='#n4249'>4249</a>
<a id='n4250' href='#n4250'>4250</a>
<a id='n4251' href='#n4251'>4251</a>
<a id='n4252' href='#n4252'>4252</a>
<a id='n4253' href='#n4253'>4253</a>
<a id='n4254' href='#n4254'>4254</a>
<a id='n4255' href='#n4255'>4255</a>
<a id='n4256' href='#n4256'>4256</a>
<a id='n4257' href='#n4257'>4257</a>
<a id='n4258' href='#n4258'>4258</a>
<a id='n4259' href='#n4259'>4259</a>
<a id='n4260' href='#n4260'>4260</a>
<a id='n4261' href='#n4261'>4261</a>
<a id='n4262' href='#n4262'>4262</a>
<a id='n4263' href='#n4263'>4263</a>
<a id='n4264' href='#n4264'>4264</a>
<a id='n4265' href='#n4265'>4265</a>
<a id='n4266' href='#n4266'>4266</a>
<a id='n4267' href='#n4267'>4267</a>
<a id='n4268' href='#n4268'>4268</a>
<a id='n4269' href='#n4269'>4269</a>
<a id='n4270' href='#n4270'>4270</a>
<a id='n4271' href='#n4271'>4271</a>
<a id='n4272' href='#n4272'>4272</a>
<a id='n4273' href='#n4273'>4273</a>
<a id='n4274' href='#n4274'>4274</a>
<a id='n4275' href='#n4275'>4275</a>
<a id='n4276' href='#n4276'>4276</a>
<a id='n4277' href='#n4277'>4277</a>
<a id='n4278' href='#n4278'>4278</a>
<a id='n4279' href='#n4279'>4279</a>
<a id='n4280' href='#n4280'>4280</a>
<a id='n4281' href='#n4281'>4281</a>
<a id='n4282' href='#n4282'>4282</a>
<a id='n4283' href='#n4283'>4283</a>
<a id='n4284' href='#n4284'>4284</a>
<a id='n4285' href='#n4285'>4285</a>
<a id='n4286' href='#n4286'>4286</a>
<a id='n4287' href='#n4287'>4287</a>
<a id='n4288' href='#n4288'>4288</a>
<a id='n4289' href='#n4289'>4289</a>
<a id='n4290' href='#n4290'>4290</a>
<a id='n4291' href='#n4291'>4291</a>
<a id='n4292' href='#n4292'>4292</a>
<a id='n4293' href='#n4293'>4293</a>
<a id='n4294' href='#n4294'>4294</a>
<a id='n4295' href='#n4295'>4295</a>
<a id='n4296' href='#n4296'>4296</a>
<a id='n4297' href='#n4297'>4297</a>
<a id='n4298' href='#n4298'>4298</a>
<a id='n4299' href='#n4299'>4299</a>
<a id='n4300' href='#n4300'>4300</a>
<a id='n4301' href='#n4301'>4301</a>
<a id='n4302' href='#n4302'>4302</a>
<a id='n4303' href='#n4303'>4303</a>
<a id='n4304' href='#n4304'>4304</a>
<a id='n4305' href='#n4305'>4305</a>
<a id='n4306' href='#n4306'>4306</a>
<a id='n4307' href='#n4307'>4307</a>
<a id='n4308' href='#n4308'>4308</a>
<a id='n4309' href='#n4309'>4309</a>
<a id='n4310' href='#n4310'>4310</a>
<a id='n4311' href='#n4311'>4311</a>
<a id='n4312' href='#n4312'>4312</a>
<a id='n4313' href='#n4313'>4313</a>
<a id='n4314' href='#n4314'>4314</a>
<a id='n4315' href='#n4315'>4315</a>
<a id='n4316' href='#n4316'>4316</a>
<a id='n4317' href='#n4317'>4317</a>
<a id='n4318' href='#n4318'>4318</a>
<a id='n4319' href='#n4319'>4319</a>
<a id='n4320' href='#n4320'>4320</a>
<a id='n4321' href='#n4321'>4321</a>
<a id='n4322' href='#n4322'>4322</a>
<a id='n4323' href='#n4323'>4323</a>
<a id='n4324' href='#n4324'>4324</a>
<a id='n4325' href='#n4325'>4325</a>
<a id='n4326' href='#n4326'>4326</a>
<a id='n4327' href='#n4327'>4327</a>
<a id='n4328' href='#n4328'>4328</a>
<a id='n4329' href='#n4329'>4329</a>
<a id='n4330' href='#n4330'>4330</a>
<a id='n4331' href='#n4331'>4331</a>
<a id='n4332' href='#n4332'>4332</a>
<a id='n4333' href='#n4333'>4333</a>
<a id='n4334' href='#n4334'>4334</a>
<a id='n4335' href='#n4335'>4335</a>
<a id='n4336' href='#n4336'>4336</a>
<a id='n4337' href='#n4337'>4337</a>
<a id='n4338' href='#n4338'>4338</a>
<a id='n4339' href='#n4339'>4339</a>
<a id='n4340' href='#n4340'>4340</a>
<a id='n4341' href='#n4341'>4341</a>
<a id='n4342' href='#n4342'>4342</a>
<a id='n4343' href='#n4343'>4343</a>
<a id='n4344' href='#n4344'>4344</a>
<a id='n4345' href='#n4345'>4345</a>
<a id='n4346' href='#n4346'>4346</a>
<a id='n4347' href='#n4347'>4347</a>
<a id='n4348' href='#n4348'>4348</a>
<a id='n4349' href='#n4349'>4349</a>
<a id='n4350' href='#n4350'>4350</a>
<a id='n4351' href='#n4351'>4351</a>
<a id='n4352' href='#n4352'>4352</a>
<a id='n4353' href='#n4353'>4353</a>
<a id='n4354' href='#n4354'>4354</a>
<a id='n4355' href='#n4355'>4355</a>
<a id='n4356' href='#n4356'>4356</a>
<a id='n4357' href='#n4357'>4357</a>
<a id='n4358' href='#n4358'>4358</a>
<a id='n4359' href='#n4359'>4359</a>
<a id='n4360' href='#n4360'>4360</a>
<a id='n4361' href='#n4361'>4361</a>
<a id='n4362' href='#n4362'>4362</a>
<a id='n4363' href='#n4363'>4363</a>
<a id='n4364' href='#n4364'>4364</a>
<a id='n4365' href='#n4365'>4365</a>
<a id='n4366' href='#n4366'>4366</a>
<a id='n4367' href='#n4367'>4367</a>
<a id='n4368' href='#n4368'>4368</a>
<a id='n4369' href='#n4369'>4369</a>
<a id='n4370' href='#n4370'>4370</a>
<a id='n4371' href='#n4371'>4371</a>
<a id='n4372' href='#n4372'>4372</a>
<a id='n4373' href='#n4373'>4373</a>
<a id='n4374' href='#n4374'>4374</a>
<a id='n4375' href='#n4375'>4375</a>
<a id='n4376' href='#n4376'>4376</a>
<a id='n4377' href='#n4377'>4377</a>
<a id='n4378' href='#n4378'>4378</a>
<a id='n4379' href='#n4379'>4379</a>
<a id='n4380' href='#n4380'>4380</a>
<a id='n4381' href='#n4381'>4381</a>
<a id='n4382' href='#n4382'>4382</a>
<a id='n4383' href='#n4383'>4383</a>
<a id='n4384' href='#n4384'>4384</a>
<a id='n4385' href='#n4385'>4385</a>
<a id='n4386' href='#n4386'>4386</a>
<a id='n4387' href='#n4387'>4387</a>
<a id='n4388' href='#n4388'>4388</a>
<a id='n4389' href='#n4389'>4389</a>
<a id='n4390' href='#n4390'>4390</a>
<a id='n4391' href='#n4391'>4391</a>
<a id='n4392' href='#n4392'>4392</a>
<a id='n4393' href='#n4393'>4393</a>
<a id='n4394' href='#n4394'>4394</a>
<a id='n4395' href='#n4395'>4395</a>
<a id='n4396' href='#n4396'>4396</a>
<a id='n4397' href='#n4397'>4397</a>
<a id='n4398' href='#n4398'>4398</a>
<a id='n4399' href='#n4399'>4399</a>
<a id='n4400' href='#n4400'>4400</a>
<a id='n4401' href='#n4401'>4401</a>
<a id='n4402' href='#n4402'>4402</a>
<a id='n4403' href='#n4403'>4403</a>
<a id='n4404' href='#n4404'>4404</a>
<a id='n4405' href='#n4405'>4405</a>
<a id='n4406' href='#n4406'>4406</a>
<a id='n4407' href='#n4407'>4407</a>
<a id='n4408' href='#n4408'>4408</a>
<a id='n4409' href='#n4409'>4409</a>
<a id='n4410' href='#n4410'>4410</a>
<a id='n4411' href='#n4411'>4411</a>
<a id='n4412' href='#n4412'>4412</a>
<a id='n4413' href='#n4413'>4413</a>
<a id='n4414' href='#n4414'>4414</a>
<a id='n4415' href='#n4415'>4415</a>
<a id='n4416' href='#n4416'>4416</a>
<a id='n4417' href='#n4417'>4417</a>
<a id='n4418' href='#n4418'>4418</a>
<a id='n4419' href='#n4419'>4419</a>
<a id='n4420' href='#n4420'>4420</a>
<a id='n4421' href='#n4421'>4421</a>
<a id='n4422' href='#n4422'>4422</a>
<a id='n4423' href='#n4423'>4423</a>
<a id='n4424' href='#n4424'>4424</a>
<a id='n4425' href='#n4425'>4425</a>
<a id='n4426' href='#n4426'>4426</a>
<a id='n4427' href='#n4427'>4427</a>
<a id='n4428' href='#n4428'>4428</a>
<a id='n4429' href='#n4429'>4429</a>
<a id='n4430' href='#n4430'>4430</a>
<a id='n4431' href='#n4431'>4431</a>
<a id='n4432' href='#n4432'>4432</a>
<a id='n4433' href='#n4433'>4433</a>
<a id='n4434' href='#n4434'>4434</a>
<a id='n4435' href='#n4435'>4435</a>
<a id='n4436' href='#n4436'>4436</a>
<a id='n4437' href='#n4437'>4437</a>
<a id='n4438' href='#n4438'>4438</a>
<a id='n4439' href='#n4439'>4439</a>
<a id='n4440' href='#n4440'>4440</a>
<a id='n4441' href='#n4441'>4441</a>
<a id='n4442' href='#n4442'>4442</a>
<a id='n4443' href='#n4443'>4443</a>
<a id='n4444' href='#n4444'>4444</a>
<a id='n4445' href='#n4445'>4445</a>
<a id='n4446' href='#n4446'>4446</a>
<a id='n4447' href='#n4447'>4447</a>
<a id='n4448' href='#n4448'>4448</a>
<a id='n4449' href='#n4449'>4449</a>
<a id='n4450' href='#n4450'>4450</a>
<a id='n4451' href='#n4451'>4451</a>
<a id='n4452' href='#n4452'>4452</a>
<a id='n4453' href='#n4453'>4453</a>
<a id='n4454' href='#n4454'>4454</a>
<a id='n4455' href='#n4455'>4455</a>
<a id='n4456' href='#n4456'>4456</a>
<a id='n4457' href='#n4457'>4457</a>
<a id='n4458' href='#n4458'>4458</a>
<a id='n4459' href='#n4459'>4459</a>
<a id='n4460' href='#n4460'>4460</a>
<a id='n4461' href='#n4461'>4461</a>
<a id='n4462' href='#n4462'>4462</a>
<a id='n4463' href='#n4463'>4463</a>
<a id='n4464' href='#n4464'>4464</a>
<a id='n4465' href='#n4465'>4465</a>
<a id='n4466' href='#n4466'>4466</a>
<a id='n4467' href='#n4467'>4467</a>
<a id='n4468' href='#n4468'>4468</a>
<a id='n4469' href='#n4469'>4469</a>
<a id='n4470' href='#n4470'>4470</a>
<a id='n4471' href='#n4471'>4471</a>
<a id='n4472' href='#n4472'>4472</a>
<a id='n4473' href='#n4473'>4473</a>
<a id='n4474' href='#n4474'>4474</a>
<a id='n4475' href='#n4475'>4475</a>
<a id='n4476' href='#n4476'>4476</a>
<a id='n4477' href='#n4477'>4477</a>
<a id='n4478' href='#n4478'>4478</a>
<a id='n4479' href='#n4479'>4479</a>
<a id='n4480' href='#n4480'>4480</a>
<a id='n4481' href='#n4481'>4481</a>
<a id='n4482' href='#n4482'>4482</a>
<a id='n4483' href='#n4483'>4483</a>
<a id='n4484' href='#n4484'>4484</a>
<a id='n4485' href='#n4485'>4485</a>
<a id='n4486' href='#n4486'>4486</a>
<a id='n4487' href='#n4487'>4487</a>
<a id='n4488' href='#n4488'>4488</a>
<a id='n4489' href='#n4489'>4489</a>
<a id='n4490' href='#n4490'>4490</a>
<a id='n4491' href='#n4491'>4491</a>
<a id='n4492' href='#n4492'>4492</a>
<a id='n4493' href='#n4493'>4493</a>
<a id='n4494' href='#n4494'>4494</a>
<a id='n4495' href='#n4495'>4495</a>
<a id='n4496' href='#n4496'>4496</a>
<a id='n4497' href='#n4497'>4497</a>
<a id='n4498' href='#n4498'>4498</a>
<a id='n4499' href='#n4499'>4499</a>
<a id='n4500' href='#n4500'>4500</a>
<a id='n4501' href='#n4501'>4501</a>
<a id='n4502' href='#n4502'>4502</a>
<a id='n4503' href='#n4503'>4503</a>
<a id='n4504' href='#n4504'>4504</a>
<a id='n4505' href='#n4505'>4505</a>
<a id='n4506' href='#n4506'>4506</a>
<a id='n4507' href='#n4507'>4507</a>
<a id='n4508' href='#n4508'>4508</a>
<a id='n4509' href='#n4509'>4509</a>
<a id='n4510' href='#n4510'>4510</a>
<a id='n4511' href='#n4511'>4511</a>
<a id='n4512' href='#n4512'>4512</a>
<a id='n4513' href='#n4513'>4513</a>
<a id='n4514' href='#n4514'>4514</a>
<a id='n4515' href='#n4515'>4515</a>
<a id='n4516' href='#n4516'>4516</a>
<a id='n4517' href='#n4517'>4517</a>
<a id='n4518' href='#n4518'>4518</a>
<a id='n4519' href='#n4519'>4519</a>
<a id='n4520' href='#n4520'>4520</a>
<a id='n4521' href='#n4521'>4521</a>
<a id='n4522' href='#n4522'>4522</a>
<a id='n4523' href='#n4523'>4523</a>
<a id='n4524' href='#n4524'>4524</a>
<a id='n4525' href='#n4525'>4525</a>
<a id='n4526' href='#n4526'>4526</a>
<a id='n4527' href='#n4527'>4527</a>
<a id='n4528' href='#n4528'>4528</a>
<a id='n4529' href='#n4529'>4529</a>
<a id='n4530' href='#n4530'>4530</a>
<a id='n4531' href='#n4531'>4531</a>
<a id='n4532' href='#n4532'>4532</a>
<a id='n4533' href='#n4533'>4533</a>
<a id='n4534' href='#n4534'>4534</a>
<a id='n4535' href='#n4535'>4535</a>
<a id='n4536' href='#n4536'>4536</a>
<a id='n4537' href='#n4537'>4537</a>
<a id='n4538' href='#n4538'>4538</a>
<a id='n4539' href='#n4539'>4539</a>
<a id='n4540' href='#n4540'>4540</a>
<a id='n4541' href='#n4541'>4541</a>
<a id='n4542' href='#n4542'>4542</a>
<a id='n4543' href='#n4543'>4543</a>
<a id='n4544' href='#n4544'>4544</a>
<a id='n4545' href='#n4545'>4545</a>
<a id='n4546' href='#n4546'>4546</a>
<a id='n4547' href='#n4547'>4547</a>
<a id='n4548' href='#n4548'>4548</a>
<a id='n4549' href='#n4549'>4549</a>
<a id='n4550' href='#n4550'>4550</a>
<a id='n4551' href='#n4551'>4551</a>
<a id='n4552' href='#n4552'>4552</a>
<a id='n4553' href='#n4553'>4553</a>
<a id='n4554' href='#n4554'>4554</a>
<a id='n4555' href='#n4555'>4555</a>
<a id='n4556' href='#n4556'>4556</a>
<a id='n4557' href='#n4557'>4557</a>
<a id='n4558' href='#n4558'>4558</a>
<a id='n4559' href='#n4559'>4559</a>
<a id='n4560' href='#n4560'>4560</a>
<a id='n4561' href='#n4561'>4561</a>
<a id='n4562' href='#n4562'>4562</a>
<a id='n4563' href='#n4563'>4563</a>
<a id='n4564' href='#n4564'>4564</a>
<a id='n4565' href='#n4565'>4565</a>
<a id='n4566' href='#n4566'>4566</a>
<a id='n4567' href='#n4567'>4567</a>
<a id='n4568' href='#n4568'>4568</a>
<a id='n4569' href='#n4569'>4569</a>
<a id='n4570' href='#n4570'>4570</a>
<a id='n4571' href='#n4571'>4571</a>
<a id='n4572' href='#n4572'>4572</a>
<a id='n4573' href='#n4573'>4573</a>
<a id='n4574' href='#n4574'>4574</a>
<a id='n4575' href='#n4575'>4575</a>
<a id='n4576' href='#n4576'>4576</a>
<a id='n4577' href='#n4577'>4577</a>
<a id='n4578' href='#n4578'>4578</a>
<a id='n4579' href='#n4579'>4579</a>
<a id='n4580' href='#n4580'>4580</a>
<a id='n4581' href='#n4581'>4581</a>
<a id='n4582' href='#n4582'>4582</a>
<a id='n4583' href='#n4583'>4583</a>
<a id='n4584' href='#n4584'>4584</a>
<a id='n4585' href='#n4585'>4585</a>
<a id='n4586' href='#n4586'>4586</a>
<a id='n4587' href='#n4587'>4587</a>
<a id='n4588' href='#n4588'>4588</a>
<a id='n4589' href='#n4589'>4589</a>
<a id='n4590' href='#n4590'>4590</a>
<a id='n4591' href='#n4591'>4591</a>
<a id='n4592' href='#n4592'>4592</a>
<a id='n4593' href='#n4593'>4593</a>
<a id='n4594' href='#n4594'>4594</a>
<a id='n4595' href='#n4595'>4595</a>
<a id='n4596' href='#n4596'>4596</a>
<a id='n4597' href='#n4597'>4597</a>
<a id='n4598' href='#n4598'>4598</a>
<a id='n4599' href='#n4599'>4599</a>
<a id='n4600' href='#n4600'>4600</a>
<a id='n4601' href='#n4601'>4601</a>
<a id='n4602' href='#n4602'>4602</a>
<a id='n4603' href='#n4603'>4603</a>
<a id='n4604' href='#n4604'>4604</a>
<a id='n4605' href='#n4605'>4605</a>
<a id='n4606' href='#n4606'>4606</a>
<a id='n4607' href='#n4607'>4607</a>
<a id='n4608' href='#n4608'>4608</a>
<a id='n4609' href='#n4609'>4609</a>
<a id='n4610' href='#n4610'>4610</a>
<a id='n4611' href='#n4611'>4611</a>
<a id='n4612' href='#n4612'>4612</a>
<a id='n4613' href='#n4613'>4613</a>
<a id='n4614' href='#n4614'>4614</a>
<a id='n4615' href='#n4615'>4615</a>
<a id='n4616' href='#n4616'>4616</a>
<a id='n4617' href='#n4617'>4617</a>
<a id='n4618' href='#n4618'>4618</a>
<a id='n4619' href='#n4619'>4619</a>
<a id='n4620' href='#n4620'>4620</a>
<a id='n4621' href='#n4621'>4621</a>
<a id='n4622' href='#n4622'>4622</a>
<a id='n4623' href='#n4623'>4623</a>
<a id='n4624' href='#n4624'>4624</a>
<a id='n4625' href='#n4625'>4625</a>
<a id='n4626' href='#n4626'>4626</a>
<a id='n4627' href='#n4627'>4627</a>
<a id='n4628' href='#n4628'>4628</a>
<a id='n4629' href='#n4629'>4629</a>
<a id='n4630' href='#n4630'>4630</a>
<a id='n4631' href='#n4631'>4631</a>
<a id='n4632' href='#n4632'>4632</a>
<a id='n4633' href='#n4633'>4633</a>
<a id='n4634' href='#n4634'>4634</a>
<a id='n4635' href='#n4635'>4635</a>
<a id='n4636' href='#n4636'>4636</a>
<a id='n4637' href='#n4637'>4637</a>
<a id='n4638' href='#n4638'>4638</a>
<a id='n4639' href='#n4639'>4639</a>
<a id='n4640' href='#n4640'>4640</a>
<a id='n4641' href='#n4641'>4641</a>
<a id='n4642' href='#n4642'>4642</a>
<a id='n4643' href='#n4643'>4643</a>
<a id='n4644' href='#n4644'>4644</a>
<a id='n4645' href='#n4645'>4645</a>
<a id='n4646' href='#n4646'>4646</a>
<a id='n4647' href='#n4647'>4647</a>
<a id='n4648' href='#n4648'>4648</a>
<a id='n4649' href='#n4649'>4649</a>
<a id='n4650' href='#n4650'>4650</a>
<a id='n4651' href='#n4651'>4651</a>
<a id='n4652' href='#n4652'>4652</a>
<a id='n4653' href='#n4653'>4653</a>
<a id='n4654' href='#n4654'>4654</a>
<a id='n4655' href='#n4655'>4655</a>
<a id='n4656' href='#n4656'>4656</a>
<a id='n4657' href='#n4657'>4657</a>
<a id='n4658' href='#n4658'>4658</a>
<a id='n4659' href='#n4659'>4659</a>
<a id='n4660' href='#n4660'>4660</a>
<a id='n4661' href='#n4661'>4661</a>
<a id='n4662' href='#n4662'>4662</a>
<a id='n4663' href='#n4663'>4663</a>
<a id='n4664' href='#n4664'>4664</a>
<a id='n4665' href='#n4665'>4665</a>
<a id='n4666' href='#n4666'>4666</a>
<a id='n4667' href='#n4667'>4667</a>
<a id='n4668' href='#n4668'>4668</a>
<a id='n4669' href='#n4669'>4669</a>
<a id='n4670' href='#n4670'>4670</a>
<a id='n4671' href='#n4671'>4671</a>
<a id='n4672' href='#n4672'>4672</a>
<a id='n4673' href='#n4673'>4673</a>
<a id='n4674' href='#n4674'>4674</a>
<a id='n4675' href='#n4675'>4675</a>
<a id='n4676' href='#n4676'>4676</a>
<a id='n4677' href='#n4677'>4677</a>
<a id='n4678' href='#n4678'>4678</a>
<a id='n4679' href='#n4679'>4679</a>
<a id='n4680' href='#n4680'>4680</a>
<a id='n4681' href='#n4681'>4681</a>
<a id='n4682' href='#n4682'>4682</a>
<a id='n4683' href='#n4683'>4683</a>
<a id='n4684' href='#n4684'>4684</a>
<a id='n4685' href='#n4685'>4685</a>
<a id='n4686' href='#n4686'>4686</a>
<a id='n4687' href='#n4687'>4687</a>
<a id='n4688' href='#n4688'>4688</a>
<a id='n4689' href='#n4689'>4689</a>
<a id='n4690' href='#n4690'>4690</a>
<a id='n4691' href='#n4691'>4691</a>
<a id='n4692' href='#n4692'>4692</a>
<a id='n4693' href='#n4693'>4693</a>
<a id='n4694' href='#n4694'>4694</a>
<a id='n4695' href='#n4695'>4695</a>
<a id='n4696' href='#n4696'>4696</a>
<a id='n4697' href='#n4697'>4697</a>
<a id='n4698' href='#n4698'>4698</a>
<a id='n4699' href='#n4699'>4699</a>
<a id='n4700' href='#n4700'>4700</a>
<a id='n4701' href='#n4701'>4701</a>
<a id='n4702' href='#n4702'>4702</a>
<a id='n4703' href='#n4703'>4703</a>
<a id='n4704' href='#n4704'>4704</a>
<a id='n4705' href='#n4705'>4705</a>
<a id='n4706' href='#n4706'>4706</a>
<a id='n4707' href='#n4707'>4707</a>
<a id='n4708' href='#n4708'>4708</a>
<a id='n4709' href='#n4709'>4709</a>
<a id='n4710' href='#n4710'>4710</a>
<a id='n4711' href='#n4711'>4711</a>
<a id='n4712' href='#n4712'>4712</a>
<a id='n4713' href='#n4713'>4713</a>
<a id='n4714' href='#n4714'>4714</a>
<a id='n4715' href='#n4715'>4715</a>
<a id='n4716' href='#n4716'>4716</a>
<a id='n4717' href='#n4717'>4717</a>
<a id='n4718' href='#n4718'>4718</a>
<a id='n4719' href='#n4719'>4719</a>
<a id='n4720' href='#n4720'>4720</a>
<a id='n4721' href='#n4721'>4721</a>
<a id='n4722' href='#n4722'>4722</a>
<a id='n4723' href='#n4723'>4723</a>
<a id='n4724' href='#n4724'>4724</a>
<a id='n4725' href='#n4725'>4725</a>
<a id='n4726' href='#n4726'>4726</a>
<a id='n4727' href='#n4727'>4727</a>
<a id='n4728' href='#n4728'>4728</a>
<a id='n4729' href='#n4729'>4729</a>
<a id='n4730' href='#n4730'>4730</a>
<a id='n4731' href='#n4731'>4731</a>
<a id='n4732' href='#n4732'>4732</a>
<a id='n4733' href='#n4733'>4733</a>
<a id='n4734' href='#n4734'>4734</a>
<a id='n4735' href='#n4735'>4735</a>
<a id='n4736' href='#n4736'>4736</a>
<a id='n4737' href='#n4737'>4737</a>
<a id='n4738' href='#n4738'>4738</a>
<a id='n4739' href='#n4739'>4739</a>
<a id='n4740' href='#n4740'>4740</a>
<a id='n4741' href='#n4741'>4741</a>
<a id='n4742' href='#n4742'>4742</a>
<a id='n4743' href='#n4743'>4743</a>
<a id='n4744' href='#n4744'>4744</a>
<a id='n4745' href='#n4745'>4745</a>
<a id='n4746' href='#n4746'>4746</a>
<a id='n4747' href='#n4747'>4747</a>
<a id='n4748' href='#n4748'>4748</a>
<a id='n4749' href='#n4749'>4749</a>
<a id='n4750' href='#n4750'>4750</a>
<a id='n4751' href='#n4751'>4751</a>
<a id='n4752' href='#n4752'>4752</a>
<a id='n4753' href='#n4753'>4753</a>
<a id='n4754' href='#n4754'>4754</a>
<a id='n4755' href='#n4755'>4755</a>
<a id='n4756' href='#n4756'>4756</a>
<a id='n4757' href='#n4757'>4757</a>
<a id='n4758' href='#n4758'>4758</a>
<a id='n4759' href='#n4759'>4759</a>
<a id='n4760' href='#n4760'>4760</a>
<a id='n4761' href='#n4761'>4761</a>
<a id='n4762' href='#n4762'>4762</a>
<a id='n4763' href='#n4763'>4763</a>
<a id='n4764' href='#n4764'>4764</a>
<a id='n4765' href='#n4765'>4765</a>
<a id='n4766' href='#n4766'>4766</a>
<a id='n4767' href='#n4767'>4767</a>
<a id='n4768' href='#n4768'>4768</a>
<a id='n4769' href='#n4769'>4769</a>
<a id='n4770' href='#n4770'>4770</a>
<a id='n4771' href='#n4771'>4771</a>
<a id='n4772' href='#n4772'>4772</a>
<a id='n4773' href='#n4773'>4773</a>
<a id='n4774' href='#n4774'>4774</a>
<a id='n4775' href='#n4775'>4775</a>
<a id='n4776' href='#n4776'>4776</a>
<a id='n4777' href='#n4777'>4777</a>
<a id='n4778' href='#n4778'>4778</a>
<a id='n4779' href='#n4779'>4779</a>
<a id='n4780' href='#n4780'>4780</a>
<a id='n4781' href='#n4781'>4781</a>
<a id='n4782' href='#n4782'>4782</a>
<a id='n4783' href='#n4783'>4783</a>
<a id='n4784' href='#n4784'>4784</a>
<a id='n4785' href='#n4785'>4785</a>
<a id='n4786' href='#n4786'>4786</a>
<a id='n4787' href='#n4787'>4787</a>
<a id='n4788' href='#n4788'>4788</a>
<a id='n4789' href='#n4789'>4789</a>
<a id='n4790' href='#n4790'>4790</a>
<a id='n4791' href='#n4791'>4791</a>
<a id='n4792' href='#n4792'>4792</a>
<a id='n4793' href='#n4793'>4793</a>
<a id='n4794' href='#n4794'>4794</a>
<a id='n4795' href='#n4795'>4795</a>
<a id='n4796' href='#n4796'>4796</a>
<a id='n4797' href='#n4797'>4797</a>
<a id='n4798' href='#n4798'>4798</a>
<a id='n4799' href='#n4799'>4799</a>
<a id='n4800' href='#n4800'>4800</a>
<a id='n4801' href='#n4801'>4801</a>
<a id='n4802' href='#n4802'>4802</a>
<a id='n4803' href='#n4803'>4803</a>
<a id='n4804' href='#n4804'>4804</a>
<a id='n4805' href='#n4805'>4805</a>
<a id='n4806' href='#n4806'>4806</a>
<a id='n4807' href='#n4807'>4807</a>
<a id='n4808' href='#n4808'>4808</a>
<a id='n4809' href='#n4809'>4809</a>
<a id='n4810' href='#n4810'>4810</a>
<a id='n4811' href='#n4811'>4811</a>
<a id='n4812' href='#n4812'>4812</a>
<a id='n4813' href='#n4813'>4813</a>
<a id='n4814' href='#n4814'>4814</a>
<a id='n4815' href='#n4815'>4815</a>
<a id='n4816' href='#n4816'>4816</a>
<a id='n4817' href='#n4817'>4817</a>
<a id='n4818' href='#n4818'>4818</a>
<a id='n4819' href='#n4819'>4819</a>
<a id='n4820' href='#n4820'>4820</a>
<a id='n4821' href='#n4821'>4821</a>
<a id='n4822' href='#n4822'>4822</a>
<a id='n4823' href='#n4823'>4823</a>
<a id='n4824' href='#n4824'>4824</a>
<a id='n4825' href='#n4825'>4825</a>
<a id='n4826' href='#n4826'>4826</a>
<a id='n4827' href='#n4827'>4827</a>
<a id='n4828' href='#n4828'>4828</a>
<a id='n4829' href='#n4829'>4829</a>
<a id='n4830' href='#n4830'>4830</a>
<a id='n4831' href='#n4831'>4831</a>
<a id='n4832' href='#n4832'>4832</a>
<a id='n4833' href='#n4833'>4833</a>
<a id='n4834' href='#n4834'>4834</a>
<a id='n4835' href='#n4835'>4835</a>
<a id='n4836' href='#n4836'>4836</a>
<a id='n4837' href='#n4837'>4837</a>
<a id='n4838' href='#n4838'>4838</a>
<a id='n4839' href='#n4839'>4839</a>
<a id='n4840' href='#n4840'>4840</a>
<a id='n4841' href='#n4841'>4841</a>
<a id='n4842' href='#n4842'>4842</a>
<a id='n4843' href='#n4843'>4843</a>
<a id='n4844' href='#n4844'>4844</a>
<a id='n4845' href='#n4845'>4845</a>
<a id='n4846' href='#n4846'>4846</a>
<a id='n4847' href='#n4847'>4847</a>
<a id='n4848' href='#n4848'>4848</a>
<a id='n4849' href='#n4849'>4849</a>
<a id='n4850' href='#n4850'>4850</a>
<a id='n4851' href='#n4851'>4851</a>
<a id='n4852' href='#n4852'>4852</a>
<a id='n4853' href='#n4853'>4853</a>
<a id='n4854' href='#n4854'>4854</a>
<a id='n4855' href='#n4855'>4855</a>
<a id='n4856' href='#n4856'>4856</a>
<a id='n4857' href='#n4857'>4857</a>
<a id='n4858' href='#n4858'>4858</a>
<a id='n4859' href='#n4859'>4859</a>
<a id='n4860' href='#n4860'>4860</a>
<a id='n4861' href='#n4861'>4861</a>
<a id='n4862' href='#n4862'>4862</a>
<a id='n4863' href='#n4863'>4863</a>
<a id='n4864' href='#n4864'>4864</a>
<a id='n4865' href='#n4865'>4865</a>
<a id='n4866' href='#n4866'>4866</a>
<a id='n4867' href='#n4867'>4867</a>
<a id='n4868' href='#n4868'>4868</a>
<a id='n4869' href='#n4869'>4869</a>
<a id='n4870' href='#n4870'>4870</a>
<a id='n4871' href='#n4871'>4871</a>
<a id='n4872' href='#n4872'>4872</a>
<a id='n4873' href='#n4873'>4873</a>
<a id='n4874' href='#n4874'>4874</a>
<a id='n4875' href='#n4875'>4875</a>
<a id='n4876' href='#n4876'>4876</a>
<a id='n4877' href='#n4877'>4877</a>
<a id='n4878' href='#n4878'>4878</a>
<a id='n4879' href='#n4879'>4879</a>
<a id='n4880' href='#n4880'>4880</a>
<a id='n4881' href='#n4881'>4881</a>
<a id='n4882' href='#n4882'>4882</a>
<a id='n4883' href='#n4883'>4883</a>
<a id='n4884' href='#n4884'>4884</a>
<a id='n4885' href='#n4885'>4885</a>
<a id='n4886' href='#n4886'>4886</a>
<a id='n4887' href='#n4887'>4887</a>
<a id='n4888' href='#n4888'>4888</a>
<a id='n4889' href='#n4889'>4889</a>
<a id='n4890' href='#n4890'>4890</a>
<a id='n4891' href='#n4891'>4891</a>
<a id='n4892' href='#n4892'>4892</a>
<a id='n4893' href='#n4893'>4893</a>
<a id='n4894' href='#n4894'>4894</a>
<a id='n4895' href='#n4895'>4895</a>
<a id='n4896' href='#n4896'>4896</a>
<a id='n4897' href='#n4897'>4897</a>
<a id='n4898' href='#n4898'>4898</a>
<a id='n4899' href='#n4899'>4899</a>
<a id='n4900' href='#n4900'>4900</a>
<a id='n4901' href='#n4901'>4901</a>
<a id='n4902' href='#n4902'>4902</a>
<a id='n4903' href='#n4903'>4903</a>
<a id='n4904' href='#n4904'>4904</a>
<a id='n4905' href='#n4905'>4905</a>
<a id='n4906' href='#n4906'>4906</a>
<a id='n4907' href='#n4907'>4907</a>
<a id='n4908' href='#n4908'>4908</a>
<a id='n4909' href='#n4909'>4909</a>
<a id='n4910' href='#n4910'>4910</a>
<a id='n4911' href='#n4911'>4911</a>
<a id='n4912' href='#n4912'>4912</a>
<a id='n4913' href='#n4913'>4913</a>
<a id='n4914' href='#n4914'>4914</a>
<a id='n4915' href='#n4915'>4915</a>
<a id='n4916' href='#n4916'>4916</a>
<a id='n4917' href='#n4917'>4917</a>
<a id='n4918' href='#n4918'>4918</a>
<a id='n4919' href='#n4919'>4919</a>
<a id='n4920' href='#n4920'>4920</a>
<a id='n4921' href='#n4921'>4921</a>
<a id='n4922' href='#n4922'>4922</a>
<a id='n4923' href='#n4923'>4923</a>
<a id='n4924' href='#n4924'>4924</a>
<a id='n4925' href='#n4925'>4925</a>
<a id='n4926' href='#n4926'>4926</a>
<a id='n4927' href='#n4927'>4927</a>
<a id='n4928' href='#n4928'>4928</a>
<a id='n4929' href='#n4929'>4929</a>
<a id='n4930' href='#n4930'>4930</a>
<a id='n4931' href='#n4931'>4931</a>
<a id='n4932' href='#n4932'>4932</a>
<a id='n4933' href='#n4933'>4933</a>
<a id='n4934' href='#n4934'>4934</a>
<a id='n4935' href='#n4935'>4935</a>
<a id='n4936' href='#n4936'>4936</a>
<a id='n4937' href='#n4937'>4937</a>
<a id='n4938' href='#n4938'>4938</a>
<a id='n4939' href='#n4939'>4939</a>
<a id='n4940' href='#n4940'>4940</a>
<a id='n4941' href='#n4941'>4941</a>
<a id='n4942' href='#n4942'>4942</a>
<a id='n4943' href='#n4943'>4943</a>
<a id='n4944' href='#n4944'>4944</a>
<a id='n4945' href='#n4945'>4945</a>
<a id='n4946' href='#n4946'>4946</a>
<a id='n4947' href='#n4947'>4947</a>
<a id='n4948' href='#n4948'>4948</a>
<a id='n4949' href='#n4949'>4949</a>
<a id='n4950' href='#n4950'>4950</a>
<a id='n4951' href='#n4951'>4951</a>
<a id='n4952' href='#n4952'>4952</a>
<a id='n4953' href='#n4953'>4953</a>
<a id='n4954' href='#n4954'>4954</a>
<a id='n4955' href='#n4955'>4955</a>
<a id='n4956' href='#n4956'>4956</a>
<a id='n4957' href='#n4957'>4957</a>
<a id='n4958' href='#n4958'>4958</a>
<a id='n4959' href='#n4959'>4959</a>
<a id='n4960' href='#n4960'>4960</a>
<a id='n4961' href='#n4961'>4961</a>
<a id='n4962' href='#n4962'>4962</a>
<a id='n4963' href='#n4963'>4963</a>
<a id='n4964' href='#n4964'>4964</a>
<a id='n4965' href='#n4965'>4965</a>
<a id='n4966' href='#n4966'>4966</a>
<a id='n4967' href='#n4967'>4967</a>
<a id='n4968' href='#n4968'>4968</a>
<a id='n4969' href='#n4969'>4969</a>
<a id='n4970' href='#n4970'>4970</a>
<a id='n4971' href='#n4971'>4971</a>
<a id='n4972' href='#n4972'>4972</a>
<a id='n4973' href='#n4973'>4973</a>
<a id='n4974' href='#n4974'>4974</a>
<a id='n4975' href='#n4975'>4975</a>
<a id='n4976' href='#n4976'>4976</a>
<a id='n4977' href='#n4977'>4977</a>
<a id='n4978' href='#n4978'>4978</a>
<a id='n4979' href='#n4979'>4979</a>
<a id='n4980' href='#n4980'>4980</a>
<a id='n4981' href='#n4981'>4981</a>
<a id='n4982' href='#n4982'>4982</a>
<a id='n4983' href='#n4983'>4983</a>
<a id='n4984' href='#n4984'>4984</a>
<a id='n4985' href='#n4985'>4985</a>
<a id='n4986' href='#n4986'>4986</a>
<a id='n4987' href='#n4987'>4987</a>
<a id='n4988' href='#n4988'>4988</a>
<a id='n4989' href='#n4989'>4989</a>
<a id='n4990' href='#n4990'>4990</a>
<a id='n4991' href='#n4991'>4991</a>
<a id='n4992' href='#n4992'>4992</a>
<a id='n4993' href='#n4993'>4993</a>
<a id='n4994' href='#n4994'>4994</a>
<a id='n4995' href='#n4995'>4995</a>
<a id='n4996' href='#n4996'>4996</a>
<a id='n4997' href='#n4997'>4997</a>
<a id='n4998' href='#n4998'>4998</a>
<a id='n4999' href='#n4999'>4999</a>
<a id='n5000' href='#n5000'>5000</a>
<a id='n5001' href='#n5001'>5001</a>
<a id='n5002' href='#n5002'>5002</a>
<a id='n5003' href='#n5003'>5003</a>
<a id='n5004' href='#n5004'>5004</a>
<a id='n5005' href='#n5005'>5005</a>
<a id='n5006' href='#n5006'>5006</a>
<a id='n5007' href='#n5007'>5007</a>
<a id='n5008' href='#n5008'>5008</a>
<a id='n5009' href='#n5009'>5009</a>
<a id='n5010' href='#n5010'>5010</a>
<a id='n5011' href='#n5011'>5011</a>
<a id='n5012' href='#n5012'>5012</a>
<a id='n5013' href='#n5013'>5013</a>
<a id='n5014' href='#n5014'>5014</a>
<a id='n5015' href='#n5015'>5015</a>
<a id='n5016' href='#n5016'>5016</a>
<a id='n5017' href='#n5017'>5017</a>
<a id='n5018' href='#n5018'>5018</a>
<a id='n5019' href='#n5019'>5019</a>
<a id='n5020' href='#n5020'>5020</a>
<a id='n5021' href='#n5021'>5021</a>
<a id='n5022' href='#n5022'>5022</a>
<a id='n5023' href='#n5023'>5023</a>
<a id='n5024' href='#n5024'>5024</a>
<a id='n5025' href='#n5025'>5025</a>
<a id='n5026' href='#n5026'>5026</a>
<a id='n5027' href='#n5027'>5027</a>
<a id='n5028' href='#n5028'>5028</a>
<a id='n5029' href='#n5029'>5029</a>
<a id='n5030' href='#n5030'>5030</a>
<a id='n5031' href='#n5031'>5031</a>
<a id='n5032' href='#n5032'>5032</a>
<a id='n5033' href='#n5033'>5033</a>
<a id='n5034' href='#n5034'>5034</a>
<a id='n5035' href='#n5035'>5035</a>
<a id='n5036' href='#n5036'>5036</a>
<a id='n5037' href='#n5037'>5037</a>
<a id='n5038' href='#n5038'>5038</a>
<a id='n5039' href='#n5039'>5039</a>
<a id='n5040' href='#n5040'>5040</a>
<a id='n5041' href='#n5041'>5041</a>
<a id='n5042' href='#n5042'>5042</a>
<a id='n5043' href='#n5043'>5043</a>
<a id='n5044' href='#n5044'>5044</a>
</pre></td>
<td class='lines'><pre><code>