STR912

Connectivity

ID Target Interface Description Initial state Input Expected output Actual output Pass/Fail
CON001 STR912 ZY1000 Telnet connection Power on, jtag target attached On console, type
telnet ip port		 Open On-Chip Debugger
>		 > telnet 10.0.0.142
Trying 10.0.0.142...
Connected to 10.0.0.142.
Escape character is '^]'.
Open On-Chip Debugger
> 		PASS
CON002 STR912 ZY1000 GDB server connection Power on, jtag target attached On GDB console, type
target remote ip:port		 Remote debugging using 10.0.0.73:3333 (gdb) tar remo 10.0.0.142:3333
Remote debugging using 10.0.0.142:3333
0x00016434 in ?? ()
(gdb) 		PASS

Reset

ID Target Interface Description Initial state Input Expected output Actual output Pass/Fail
RES001 STR912 ZY1000 Reset halt on a blank target Erase all the content of the flash Connect via the telnet interface and type
reset halt		 Reset should return without error and the output should contain
target state: halted		 > reset halt
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
> 		PASS
RES002 STR912 ZY1000 Reset init on a blank target Erase all the content of the flash Connect via the telnet interface and type
reset init		 Reset should return without error and the output should contain
executing reset script 'name_of_the_script'		 > reset init
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
cleared protection for sectors 0 through 7 on flash bank 0
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
> 		PASS
RES003 STR912 ZY1000 Reset after a power cycle of the target Reset the target then power cycle the target Connect via the telnet interface and type
reset halt after the power was detected		 Reset should return without error and the output should contain
target state: halted		 nsed nSRST asserted.
nsed power dropout.
nsed power restore.
RCLK - adaptive
SRST took 85ms to deassert
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
cleared protection for sectors 0 through 7 on flash bank 0
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
> reset halt
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
> 		PASS
RES004 STR912 ZY1000 Reset halt on a blank target where reset halt is supported Erase all the content of the flash Connect via the telnet interface and type
reset halt		 Reset should return without error and the output should contain
target state: halted
pc = 0		 > reset halt
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)
JTAG Tap/device matched
JTAG tap: str912.cpu tap/device found: 0x25966041 (Manufacturer: 0x020, Part: 0x5966, Version: 0x2)
JTAG Tap/device matched
JTAG tap: str912.bs tap/device found: 0x2457f041 (Manufacturer: 0x020, Part: 0x457f, Version: 0x2)
JTAG Tap/device matched
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
> 		PASS
RES005 STR912 ZY1000 Reset halt on a blank target using return clock Erase all the content of the flash, set the configuration script to use RCLK Connect via the telnet interface and type
reset halt		 Reset should return without error and the output should contain
target state: halted		 > reset halt
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
> 		PASS

JTAG Speed

ID Target ZY1000 Description Initial state Input Expected output Actual output Pass/Fail
SPD001 STR912 ZY1000 16MHz on normal operation Reset init the target according to RES002 Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32		 The command should run without any errors. If any JTAG checking errors happen, the test failed > jtag_khz 16000
jtag_speed 4 => JTAG clk=16.000000
16000 kHz
ThumbEE -- incomplete support
target state: halted
target halted in ThumbEE state due to debug-request, current mode: System
cpsr: 0xfdfdffff pc: 0xfdfdfff9
> mdw 0 32
0x00000000: 00000000 00000000 ffffffff ffffffff 00000001 ffffffff 00000001 ffffffff
0x00000020: 00000001 00000001 00000001 00000001 00000001 fffffffe fffffffe 00000001
0x00000040: fffffffe 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x00000060: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000001 00000000
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
ThumbEE -- incomplete support
target state: halted
target halted in ThumbEE state due to debug-request, current mode: System
cpsr: 0xffffffff pc: 0xfffffff8
> 		FAIL
SPD002 STR912 ZY1000 8MHz on normal operation Reset init the target according to RES002 Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32		 The command should run without any errors. If any JTAG checking errors happen, the test failed > jtag_khz 8000
jtag_speed 8 => JTAG clk=8.000000
8000 kHz
> halt
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
Command handler execution failed
in procedure 'halt' called at file "command.c", line 647
called at file "command.c", line 361
Halt timed out, wake up GDB.
> 		FAIL
SPD003 STR912 ZY1000 4MHz on normal operation Reset init the target according to RES002 Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32		 The command should run without any errors. If any JTAG checking errors happen, the test failed > jtag_khz 4000
jtag_speed 16 => JTAG clk=4.000000
4000 kHz
> halt
> mdw 0 32
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
> 		PASS
SPD004 STR912 ZY1000 2MHz on normal operation Reset init the target according to RES002 Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32		 The command should run without any errors. If any JTAG checking errors happen, the test failed > jtag_khz 2000
jtag_speed 32 => JTAG clk=2.000000
2000 kHz
> halt
> mdw 0 32
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
> 		PASS
SPD005 STR912 ZY1000 RCLK on normal operation Reset init the target according to RES002 Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32		 The command should run without any errors. If any JTAG checking errors happen, the test failed > jtag_khz 0
RCLK - adaptive
> halt
> mdw 0 32
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
> 		PASS

Debugging

ID Target Interface Description Initial state Input Expected output Actual output Pass/Fail
DBG001 STR912 ZY1000 Load is working Reset init is working, RAM is accesible, GDB server is started On the console of the OS:
arm-elf-gdb test_ram.elf
(gdb) target remote ip:port
(gdb) load 		Load should return without error, typical output looks like:
Loading section .text, size 0x14c lma 0x0
Start address 0x40, load size 332
Transfer rate: 180 bytes/sec, 332 bytes/write.
 		(gdb) load
Loading section .text, size 0x1a0 lma 0x4000000
Loading section .rodata, size 0x4 lma 0x40001a0
Start address 0x4000000, load size 420
Transfer rate: 29 KB/sec, 210 bytes/write.
(gdb) 		PASS
DBG002 STR912 ZY1000 Software breakpoint Load the test_ram.elf application, use instructions from GDB001 In the GDB console:
(gdb) monitor gdb_breakpoint_override soft
force soft breakpoints
(gdb) break main
Breakpoint 1 at 0xec: file src/main.c, line 71.
(gdb) continue
Continuing. 		The software breakpoint should be reached, a typical output looks like:
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x000000ec

Breakpoint 1, main () at src/main.c:71
71 DWORD a = 1; 		(gdb) monitor gdb_breakpoint_override soft
force soft breakpoints
Current language: auto
The current source language is "auto; currently asm".
(gdb) break main
Breakpoint 1 at 0x4000144: file src/main.c, line 69.
(gdb) c
Continuing.

Breakpoint 1, main () at src/main.c:69
warning: Source file is more recent than executable.
69 DWORD a = 1;
Current language: auto
The current source language is "auto; currently c".
(gdb) 		PASS
DBG003 STR912 ZY1000 Single step in a RAM application Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 In GDB, type
(gdb) step		 The next instruction should be reached, typical output:
(gdb) step
target state: halted
target halted in ARM state due to single step, current mode: Abort
cpsr: 0x20000097 pc: 0x000000f0
target state: halted
target halted in ARM state due to single step, current mode: Abort
cpsr: 0x20000097 pc: 0x000000f4
72 DWORD b = 2; 		(gdb) step
70 DWORD b = 2;
(gdb)
 		PASS
DBG004 STR912 ZY1000 Software break points are working after a reset Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 In GDB, type
(gdb) monitor reset init
(gdb) load
(gdb) continue
 The breakpoint should be reached, typical output:
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x000000ec

Breakpoint 1, main () at src/main.c:71
71 DWORD a = 1; 		(gdb) monitor reset init
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
cleared protection for sectors 0 through 7 on flash bank 0
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
(gdb) load
Loading section .text, size 0x1a0 lma 0x4000000
Loading section .rodata, size 0x4 lma 0x40001a0
Start address 0x4000000, load size 420
Transfer rate: 25 KB/sec, 210 bytes/write.
(gdb) c
Continuing.

Breakpoint 1, main () at src/main.c:69
69 DWORD a = 1;
(gdb) 		PASS
DBG005 STR912 ZY1000 Hardware breakpoint Flash the test_rom.elf application. Make this test after FLA004 has passed Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
(gdb) monitor reset init
(gdb) load
Loading section .text, size 0x194 lma 0x100000
Start address 0x100040, load size 404
Transfer rate: 179 bytes/sec, 404 bytes/write.
(gdb) monitor gdb_breakpoint_override hard
force hard breakpoints
(gdb) break main
Breakpoint 1 at 0x100134: file src/main.c, line 69.
(gdb) continue
 		The breakpoint should be reached, typical output:
Continuing.

Breakpoint 1, main () at src/main.c:69
69 DWORD a = 1;
 		(gdb) monitor reset init
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
cleared protection for sectors 0 through 7 on flash bank 0
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
(gdb) load
Loading section .text, size 0x1a0 lma 0x0
Loading section .rodata, size 0x4 lma 0x1a0
Start address 0x0, load size 420
Transfer rate: 426 bytes/sec, 210 bytes/write.
(gdb) monitor gdb_breakpoint_override hard
force hard breakpoints
(gdb) break main
Breakpoint 1 at 0x144: file src/main.c, line 69.
(gdb) continue
Continuing.
Note: automatically using hardware breakpoints for read-only addresses.

Breakpoint 1, main () at src/main.c:69
warning: Source file is more recent than executable.
69 DWORD a = 1;
Current language: auto
The current source language is "auto; currently c".
(gdb) 		PASS
DBG006 STR912 ZY1000 Hardware breakpoint is set after a reset Follow the instructions to flash and insert a hardware breakpoint from DBG005 In GDB, type
(gdb) monitor reset
(gdb) monitor reg pc 0x100000
pc (/32): 0x00100000
(gdb) continue
where the value inserted in PC is the start address of the application 		The breakpoint should be reached, typical output:
Continuing.

Breakpoint 1, main () at src/main.c:69
69 DWORD a = 1;
 		(gdb) monitor reset init
RCLK - adaptive
SRST took 2ms to deassert
JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
Trying to use configured scan chain anyway...
Bypassing JTAG setup events due to errors
SRST took 2ms to deassert
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
cleared protection for sectors 0 through 7 on flash bank 0
NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
(gdb) c
Continuing.

Breakpoint 1, main () at src/main.c:69
69 DWORD a = 1;
(gdb) 		PASS
DBG007 STR912 ZY1000 Single step in ROM Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
(gdb) monitor reset
(gdb) load
Loading section .text, size 0x194 lma 0x100000
Start address 0x100040, load size 404
Transfer rate: 179 bytes/sec, 404 bytes/write.
(gdb) monitor arm7_9 force_hw_bkpts enable
force hardware breakpoints enabled
(gdb) break main
Breakpoint 1 at 0x100134: file src/main.c, line 69.
(gdb) continue
Continuing.

Breakpoint 1, main () at src/main.c:69
69 DWORD a = 1;
(gdb) step 		The breakpoint should be reached, typical output:
target state: halted
target halted in ARM state due to single step, current mode: Supervisor
cpsr: 0x60000013 pc: 0x0010013c
70 DWORD b = 2;
 		(gdb) c
Continuing.

Breakpoint 2, main () at src/main.c:69
69 DWORD a = 1;
Current language: auto
The current source language is "auto; currently c".
(gdb) step
70 DWORD b = 2;
(gdb) 		PASS

RAM access

Note: these tests are not designed to test/debug the target, but to test functionalities!
ID Target Interface Description Initial state Input Expected output Actual output Pass/Fail
RAM001 STR912 ZY1000 32 bit Write/read RAM Reset init is working On the telnet interface
> mww ram_address 0xdeadbeef 16
> mdw ram_address 32 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
> mww 0x0 0xdeadbeef 16
> mdw 0x0 32
0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
 		> mww 0x4000000 0xdeadbeef 16
> mdw 0x4000000 32
0x04000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x04000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x04000040: e580100c e3a01802 e5801010 e3a01018 e5801018 e59f00a8 e59f10a8 e5801000
0x04000060: e3a00806 ee2f0f11 e321f0d7 e59fd098 e321f0db e59fd094 e321f0d3 e59fd090
> 		PASS
RAM002 STR912 ZY1000 16 bit Write/read RAM Reset init is working On the telnet interface
> mwh ram_address 0xbeef 16
> mdh ram_address 32 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
> mwh 0x0 0xbeef 16
> mdh 0x0 32
0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
> 		> mwh 0x4000000 0xbeef 16
> mdh 0x4000000 32
0x04000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
0x04000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead
> 		PASS
RAM003 STR912 ZY1000 8 bit Write/read RAM Reset init is working On the telnet interface
> mwb ram_address 0xab 16
> mdb ram_address 32 		The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
> mwb ram_address 0xab 16
> mdb ram_address 32
0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 		> mwb 0x4000000 0xab 16
> mdb 0x4000000 32
0x04000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
> 		PASS

Flash access

ID Target Interface Description Initial state Input Expected output Actual output Pass/Fail
FLA001 STR912 ZY1000 Flash probe Reset init is working On the telnet interface:
> flash probe 0 		The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
flash 'ecosflash' found at 0x01000000 		> flash probe 0
flash 'str9x' found at 0x00000000
> 		PASS
FLA002 STR912 ZY1000 flash fillw Reset init is working, flash is probed On the telnet interface
> flash fillw 0x1000000 0xdeadbeef 16 		The commands should execute without error. The output looks like:
wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
To verify the contents of the flash:
> mdw 0x1000000 32
0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 		> flash fillw 0x0 0xdeadbeef 16
wrote 64 bytes to 0x00000000 in 0.020000s (3.125 kb/s)
> mdw 0 32
0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
> 		PASS
FLA003 STR912 ZY1000 Flash erase Reset init is working, flash is probed On the telnet interface
> flash erase_address 0x1000000 0x20000 		The commands should execute without error.
erased address 0x01000000 length 131072 in 4.970000s
 To check that the flash has been erased, read at different addresses. The result should always be 0xff.
> mdw 0x1000000 32
0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 		> flash erase_address 0 0x20000
erased address 0x00000000 (length 131072) in 1.970000s (64.975 kb/s)
> mdw 0 32
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
> 		PASS
FLA004 STR912 ZY1000 Entire flash erase Reset init is working, flash is probed On the telnet interface
> flash erase_address 0x0 0x80000 		The commands should execute without error.
erased address 0x01000000 length 8192 in 4.970000s
 To check that the flash has been erased, read at different addresses. The result should always be 0xff.
> mdw 0x1000000 32
0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 		> flash erase_address 0 0x80000
erased address 0x00000000 length 524288 in 1.020000s

> mdw 0 32
0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 		PASS
FLA005 STR912 ZY1000 Loading to flash from GDB Reset init is working, flash is probed, connectivity to GDB server is working Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
(gdb) target remote ip:port
(gdb) monitor reset
(gdb) load
Loading section .text, size 0x194 lma 0x100000
Start address 0x100040, load size 404
Transfer rate: 179 bytes/sec, 404 bytes/write. (gdb) monitor verify_image path_to_elf_file 		The output should look like:
verified 404 bytes in 5.060000s
The failure message is something like:
Verify operation failed address 0x00200000. Was 0x00 instead of 0x18 		(gdb) load
Loading section .text, size 0x1a0 lma 0x0
Loading section .rodata, size 0x4 lma 0x1a0
Start address 0x0, load size 420
Transfer rate: 425 bytes/sec, 210 bytes/write.
(gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf
verified 420 bytes in 0.350000s (1.172 kb/s)
(gdb) 		PASS