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| author | Samuel Ortiz <sameo@linux.intel.com> | 2008-10-21 16:25:42 +0200 |
|---|---|---|
| committer | Samuel Ortiz <sameo@openedhand.com> | 2008-10-21 16:26:53 +0200 |
| commit | e169b23e66575856c5712b8f2162e305d8560d6b (patch) | |
| tree | 44b2549bfc20563c79808b92db16baf7101adda1 /meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch | |
| parent | e5c53ce035eb36fc1b416e9971582a45754844be (diff) | |
| download | openembedded-core-e169b23e66575856c5712b8f2162e305d8560d6b.tar.gz openembedded-core-e169b23e66575856c5712b8f2162e305d8560d6b.tar.bz2 openembedded-core-e169b23e66575856c5712b8f2162e305d8560d6b.tar.xz openembedded-core-e169b23e66575856c5712b8f2162e305d8560d6b.zip | |
linux-moblin: Add 2.6.27 moblin kernel
This will be the default moblin kernel.
We also moved the 2.6.27-rc* kernels to meta-moblin.
Diffstat (limited to 'meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch')
| -rw-r--r-- | meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch b/meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch new file mode 100644 index 000000000..f5481d7d8 --- /dev/null +++ b/meta-moblin/packages/linux/linux-moblin-2.6.27/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch @@ -0,0 +1,23 @@ +commit 930469634910fa87c21f0a7423c98b270d35d8c6 +Author: Eric Anholt <eric@anholt.net> +Date: Mon Sep 15 13:13:34 2008 -0700 + + drm: G33-class hardware has a newer 965-style MCH (no DCC register). + + Fixes bad software fallback rendering in Mesa in dual-channel configurations. + + d9a2470012588dc5313a5ac8bb2f03575af00e99 + +diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c +index 0c1b3a0..6b3f1e4 100644 +--- a/drivers/gpu/drm/i915/i915_gem_tiling.c ++++ b/drivers/gpu/drm/i915/i915_gem_tiling.c +@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) + */ + swizzle_x = I915_BIT_6_SWIZZLE_NONE; + swizzle_y = I915_BIT_6_SWIZZLE_NONE; +- } else if (!IS_I965G(dev) || IS_I965GM(dev)) { ++ } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { + uint32_t dcc; + + /* On 915-945 and GM965, channel interleave by the CPU is |