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| author | Samuel Ortiz <sameo@openedhand.com> | 2008-10-09 17:00:45 +0000 |
|---|---|---|
| committer | Samuel Ortiz <sameo@openedhand.com> | 2008-10-09 17:00:45 +0000 |
| commit | d89d52d3ec86cf95dd93bb78c9b0ab537200e180 (patch) | |
| tree | ac2667cd2ffa466be3f333c032045b9e3a8805d2 /meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch | |
| parent | 3d40acdf3e5e6d7da75862fa309b58f0d555141a (diff) | |
| download | openembedded-core-d89d52d3ec86cf95dd93bb78c9b0ab537200e180.tar.gz openembedded-core-d89d52d3ec86cf95dd93bb78c9b0ab537200e180.tar.bz2 openembedded-core-d89d52d3ec86cf95dd93bb78c9b0ab537200e180.tar.xz openembedded-core-d89d52d3ec86cf95dd93bb78c9b0ab537200e180.zip | |
linux-moblin: 2.6.27-rc6 kernel
That includes the fastboot patches. An eee boots in 10s with that
kernel.
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@5470 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch')
| -rw-r--r-- | meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch b/meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch new file mode 100644 index 000000000..f5481d7d8 --- /dev/null +++ b/meta/packages/linux/linux-moblin-2.6.27-rc6/0021-drm-G33-class-hardware-has-a-newer-965-style-MCH-n.patch @@ -0,0 +1,23 @@ +commit 930469634910fa87c21f0a7423c98b270d35d8c6 +Author: Eric Anholt <eric@anholt.net> +Date: Mon Sep 15 13:13:34 2008 -0700 + + drm: G33-class hardware has a newer 965-style MCH (no DCC register). + + Fixes bad software fallback rendering in Mesa in dual-channel configurations. + + d9a2470012588dc5313a5ac8bb2f03575af00e99 + +diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c +index 0c1b3a0..6b3f1e4 100644 +--- a/drivers/gpu/drm/i915/i915_gem_tiling.c ++++ b/drivers/gpu/drm/i915/i915_gem_tiling.c +@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) + */ + swizzle_x = I915_BIT_6_SWIZZLE_NONE; + swizzle_y = I915_BIT_6_SWIZZLE_NONE; +- } else if (!IS_I965G(dev) || IS_I965GM(dev)) { ++ } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { + uint32_t dcc; + + /* On 915-945 and GM965, channel interleave by the CPU is |