gcc-4.6.0: Bring in patches from FSF 4.6 branch

This brings in new patches from 4.6 release branch
updates the comment section of existing branch to not
contain patch numbers.

Tested build on qemu for arm ppc mips x86 and x86_64

Signed-off-by: Khem Raj <raj.khem@gmail.com>

1 files changed, 126 insertions, 0 deletions

diff --git a/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch
new file mode 100644
index 000000000..4e133ff66
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch
@@ -0,0 +1,126 @@
+From ad1e75ff0d2af88f3845d34f3f944a9211f7d9ec Mon Sep 17 00:00:00 2001
+From: nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Tue, 17 May 2011 08:46:51 +0000
+Subject: [PATCH] 	* config/rx/rx.md: Add peephole to remove redundant extensions
+ 	after loads.
+ 	(bitset_in_memory): Use rx_restricted_mem_operand.
+ 	(bitinvert_in_memory): Likewise.
+ 	(bitclr_in_memory): Likewise.
+
+	* config/rx/rx.md: Add peepholes to match a register move followed
+	by a comparison of the moved register.  Replace these with an
+	addition of zero that does both actions in one instruction.
+
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@173823 138bc75d-0d04-0410-961f-82ee72b054a4
+
+index 641f1d4..742c0f9 100644
+--- a/gcc/config/rx/rx.md
++++ b/gcc/config/rx/rx.md
+@@ -904,6 +904,39 @@
+    (set_attr "length"   "3,4,5,6,7,6")]
+ )
+ 
++;; Peepholes to match:
++;;   (set (reg A) (reg B))
++;;   (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
++;; and replace them with the addsi3_flags pattern, using an add
++;; of zero to copy the register and set the condition code bits.
++(define_peephole2
++  [(set (match_operand:SI 0 "register_operand")
++        (match_operand:SI 1 "register_operand"))
++   (set (reg:CC CC_REG)
++        (compare:CC (match_dup 0)
++                    (const_int 0)))]
++  ""
++  [(parallel [(set (match_dup 0)
++		   (plus:SI (match_dup 1) (const_int 0)))
++	      (set (reg:CC_ZSC CC_REG)
++		   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
++				   (const_int 0)))])]
++)
++
++(define_peephole2
++  [(set (match_operand:SI 0 "register_operand")
++        (match_operand:SI 1 "register_operand"))
++   (set (reg:CC CC_REG)
++        (compare:CC (match_dup 1)
++                    (const_int 0)))]
++  ""
++  [(parallel [(set (match_dup 0)
++		   (plus:SI (match_dup 1) (const_int 0)))
++	      (set (reg:CC_ZSC CC_REG)
++		   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
++				   (const_int 0)))])]
++)
++
+ (define_expand "adddi3"
+   [(set (match_operand:DI          0 "register_operand")
+ 	(plus:DI (match_operand:DI 1 "register_operand")
+@@ -1668,6 +1701,35 @@
+ 		    (extend_types:SI (match_dup 1))))]
+ )
+ 
++;; Convert:
++;;   (set (reg1) (sign_extend (mem))
++;;   (set (reg2) (zero_extend (reg1))
++;; into
++;;   (set (reg2) (zero_extend (mem)))
++(define_peephole2
++  [(set (match_operand:SI                              0 "register_operand")
++	(sign_extend:SI (match_operand:small_int_modes 1 "memory_operand")))
++   (set (match_operand:SI                              2 "register_operand")
++	(zero_extend:SI (match_operand:small_int_modes 3 "register_operand")))]
++  "REGNO (operands[0]) == REGNO (operands[3])
++   && (REGNO (operands[0]) == REGNO (operands[2])
++       || peep2_regno_dead_p (2, REGNO (operands[0])))"
++  [(set (match_dup 2)
++	(zero_extend:SI (match_dup 1)))]
++)
++
++;; Remove the redundant sign extension from:
++;;   (set (reg) (extend (mem)))
++;;   (set (reg) (extend (reg)))
++(define_peephole2
++  [(set (match_operand:SI                               0 "register_operand")
++	(extend_types:SI (match_operand:small_int_modes 1 "memory_operand")))
++   (set (match_dup 0)
++	(extend_types:SI (match_operand:small_int_modes 2 "register_operand")))]
++  "REGNO (operands[0]) == REGNO (operands[2])"
++  [(set (match_dup 0) (extend_types:SI (match_dup 1)))]
++)
++
+ (define_insn "*comparesi3_<extend_types:code><small_int_modes:mode>"
+   [(set (reg:CC CC_REG)
+ 	(compare:CC (match_operand:SI                               0 "register_operand" "=r")
+@@ -1769,7 +1831,7 @@
+ )
+ 
+ (define_insn "*bitset_in_memory"
+-  [(set (match_operand:QI                    0 "memory_operand" "+Q")
++  [(set (match_operand:QI                    0 "rx_restricted_mem_operand" "+Q")
+ 	(ior:QI (ashift:QI (const_int 1)
+ 			   (match_operand:QI 1 "nonmemory_operand" "ri"))
+ 		(match_dup 0)))]
+@@ -1790,7 +1852,7 @@
+ )
+ 
+ (define_insn "*bitinvert_in_memory"
+-  [(set (match_operand:QI 0 "memory_operand" "+Q")
++  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+ 	(xor:QI (ashift:QI (const_int 1)
+ 			   (match_operand:QI 1 "nonmemory_operand" "ri"))
+ 		(match_dup 0)))]
+@@ -1813,7 +1875,7 @@
+ )
+ 
+ (define_insn "*bitclr_in_memory"
+-  [(set (match_operand:QI 0 "memory_operand" "+Q")
++  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+ 	(and:QI (not:QI
+ 		  (ashift:QI
+ 		    (const_int 1)
+-- 
+1.7.0.4
+