diff options
Diffstat (limited to 'meta-moblin/packages/linux/linux-moblin-2.6.27/0004-i915-Use-more-consistent-names-for-regs-and-store.patch')
| -rw-r--r-- | meta-moblin/packages/linux/linux-moblin-2.6.27/0004-i915-Use-more-consistent-names-for-regs-and-store.patch | 2746 |
1 files changed, 0 insertions, 2746 deletions
diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.27/0004-i915-Use-more-consistent-names-for-regs-and-store.patch b/meta-moblin/packages/linux/linux-moblin-2.6.27/0004-i915-Use-more-consistent-names-for-regs-and-store.patch deleted file mode 100644 index f7a310ea6..000000000 --- a/meta-moblin/packages/linux/linux-moblin-2.6.27/0004-i915-Use-more-consistent-names-for-regs-and-store.patch +++ /dev/null @@ -1,2746 +0,0 @@ -commit 573e91575687018b4307f53a50f4da0084dbdf3d -Author: Jesse Barnes <jbarnes@virtuousgeek.org> -Date: Tue Jul 29 11:54:06 2008 -0700 - - i915: Use more consistent names for regs, and store them in a separate file. - - Signed-off-by: Eric Anholt <eric@anholt.net> - Signed-off-by: Dave Airlie <airlied@redhat.com> - -diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c -index 01a869b..7be580b 100644 ---- a/drivers/gpu/drm/i915/i915_dma.c -+++ b/drivers/gpu/drm/i915/i915_dma.c -@@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) - { - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); -- u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; -+ u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - int i; - - for (i = 0; i < 10000; i++) { -- ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; -+ ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; -@@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm_device * dev) - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); - -- ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; -- ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; -+ ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; -+ ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; -@@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_device * dev) - drm_pci_free(dev, dev_priv->status_page_dmah); - dev_priv->status_page_dmah = NULL; - /* Need to rewrite hardware status page */ -- I915_WRITE(0x02080, 0x1ffff000); -+ I915_WRITE(HWS_PGA, 0x1ffff000); - } - - if (dev_priv->status_gfx_addr) { - dev_priv->status_gfx_addr = 0; - drm_core_ioremapfree(&dev_priv->hws_map, dev); -- I915_WRITE(0x2080, 0x1ffff000); -+ I915_WRITE(HWS_PGA, 0x1ffff000); - } - - return 0; -@@ -170,7 +170,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) - dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; - - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); -- I915_WRITE(0x02080, dev_priv->dma_status_page); -+ I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - } - DRM_DEBUG("Enabled hardware status page\n"); - return 0; -@@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_device * dev) - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - if (dev_priv->status_gfx_addr != 0) -- I915_WRITE(0x02080, dev_priv->status_gfx_addr); -+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - else -- I915_WRITE(0x02080, dev_priv->dma_status_page); -+ I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); - - return 0; -@@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct drm_device *dev) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; - - BEGIN_LP_RING(4); -- OUT_RING(CMD_STORE_DWORD_IDX); -- OUT_RING(20); -+ OUT_RING(MI_STORE_DWORD_INDEX); -+ OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); -@@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm_device * dev) - i915_kernel_lost_context(dev); - - BEGIN_LP_RING(2); -- OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); -+ OUT_RING(MI_FLUSH | MI_READ_FLUSH); - OUT_RING(0); - ADVANCE_LP_RING(); - -@@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm_device * dev) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; - - BEGIN_LP_RING(4); -- OUT_RING(CMD_STORE_DWORD_IDX); -- OUT_RING(20); -+ OUT_RING(MI_STORE_DWORD_INDEX); -+ OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); -@@ -728,8 +728,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data, - dev_priv->hw_status_page = dev_priv->hws_map.handle; - - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); -- I915_WRITE(0x02080, dev_priv->status_gfx_addr); -- DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n", -+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); -+ DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", - dev_priv->status_gfx_addr); - DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); - return 0; -diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c -index 93aed1c..6c99aab 100644 ---- a/drivers/gpu/drm/i915/i915_drv.c -+++ b/drivers/gpu/drm/i915/i915_drv.c -@@ -279,13 +279,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) - dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); - dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); - dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); -- dev_priv->saveDSPABASE = I915_READ(DSPABASE); -+ dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); - if (IS_I965G(dev)) { - dev_priv->saveDSPASURF = I915_READ(DSPASURF); - dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); - } - i915_save_palette(dev, PIPE_A); -- dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT); -+ dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); - - /* Pipe & plane B info */ - dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); -@@ -307,13 +307,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) - dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); - dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); - dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); -- dev_priv->saveDSPBBASE = I915_READ(DSPBBASE); -+ dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); - if (IS_I965GM(dev) || IS_IGD_GM(dev)) { - dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); - dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); - } - i915_save_palette(dev, PIPE_B); -- dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT); -+ dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); - - /* CRT state */ - dev_priv->saveADPA = I915_READ(ADPA); -@@ -328,9 +328,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) - dev_priv->saveLVDS = I915_READ(LVDS); - if (!IS_I830(dev) && !IS_845G(dev)) - dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); -- dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON); -- dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF); -- dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE); -+ dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); -+ dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); -+ dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); - - /* FIXME: save TV & SDVO state */ - -@@ -341,19 +341,19 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) - dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); - - /* Interrupt state */ -- dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R); -- dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R); -- dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R); -+ dev_priv->saveIIR = I915_READ(IIR); -+ dev_priv->saveIER = I915_READ(IER); -+ dev_priv->saveIMR = I915_READ(IMR); - - /* VGA state */ -- dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); -- dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); -- dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV); -+ dev_priv->saveVGA0 = I915_READ(VGA0); -+ dev_priv->saveVGA1 = I915_READ(VGA1); -+ dev_priv->saveVGA_PD = I915_READ(VGA_PD); - dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); - - /* Clock gating state */ - dev_priv->saveD_STATE = I915_READ(D_STATE); -- dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); -+ dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); - - /* Cache mode state */ - dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); -@@ -363,7 +363,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state) - - /* Scratch space */ - for (i = 0; i < 16; i++) { -- dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2)); -+ dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); - dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); - } - for (i = 0; i < 3; i++) -@@ -424,7 +424,7 @@ static int i915_resume(struct drm_device *dev) - I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); - I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); - I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); -- I915_WRITE(DSPABASE, dev_priv->saveDSPABASE); -+ I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); - I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); - if (IS_I965G(dev)) { - I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); -@@ -436,7 +436,7 @@ static int i915_resume(struct drm_device *dev) - i915_restore_palette(dev, PIPE_A); - /* Enable the plane */ - I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); -- I915_WRITE(DSPABASE, I915_READ(DSPABASE)); -+ I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); - - /* Pipe & plane B info */ - if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { -@@ -466,7 +466,7 @@ static int i915_resume(struct drm_device *dev) - I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); - I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); - I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); -- I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE); -+ I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); - I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); - if (IS_I965G(dev)) { - I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); -@@ -478,7 +478,7 @@ static int i915_resume(struct drm_device *dev) - i915_restore_palette(dev, PIPE_B); - /* Enable the plane */ - I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); -- I915_WRITE(DSPBBASE, I915_READ(DSPBBASE)); -+ I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); - - /* CRT state */ - I915_WRITE(ADPA, dev_priv->saveADPA); -@@ -493,9 +493,9 @@ static int i915_resume(struct drm_device *dev) - - I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); - I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); -- I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON); -- I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF); -- I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE); -+ I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); -+ I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); -+ I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); - I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); - - /* FIXME: restore TV & SDVO state */ -@@ -508,14 +508,14 @@ static int i915_resume(struct drm_device *dev) - - /* VGA state */ - I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); -- I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0); -- I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1); -- I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV); -+ I915_WRITE(VGA0, dev_priv->saveVGA0); -+ I915_WRITE(VGA1, dev_priv->saveVGA1); -+ I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); - udelay(150); - - /* Clock gating state */ - I915_WRITE (D_STATE, dev_priv->saveD_STATE); -- I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); -+ I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS); - - /* Cache mode state */ - I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); -@@ -524,7 +524,7 @@ static int i915_resume(struct drm_device *dev) - I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); - - for (i = 0; i < 16; i++) { -- I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]); -+ I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); - I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); - } - for (i = 0; i < 3; i++) -diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h -index 2d441d3..afb51a3 100644 ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h -@@ -30,6 +30,8 @@ - #ifndef _I915_DRV_H_ - #define _I915_DRV_H_ - -+#include "i915_reg.h" -+ - /* General customization: - */ - -@@ -138,7 +140,7 @@ typedef struct drm_i915_private { - u32 saveDSPASTRIDE; - u32 saveDSPASIZE; - u32 saveDSPAPOS; -- u32 saveDSPABASE; -+ u32 saveDSPAADDR; - u32 saveDSPASURF; - u32 saveDSPATILEOFF; - u32 savePFIT_PGM_RATIOS; -@@ -159,24 +161,24 @@ typedef struct drm_i915_private { - u32 saveDSPBSTRIDE; - u32 saveDSPBSIZE; - u32 saveDSPBPOS; -- u32 saveDSPBBASE; -+ u32 saveDSPBADDR; - u32 saveDSPBSURF; - u32 saveDSPBTILEOFF; -- u32 saveVCLK_DIVISOR_VGA0; -- u32 saveVCLK_DIVISOR_VGA1; -- u32 saveVCLK_POST_DIV; -+ u32 saveVGA0; -+ u32 saveVGA1; -+ u32 saveVGA_PD; - u32 saveVGACNTRL; - u32 saveADPA; - u32 saveLVDS; -- u32 saveLVDSPP_ON; -- u32 saveLVDSPP_OFF; -+ u32 savePP_ON_DELAYS; -+ u32 savePP_OFF_DELAYS; - u32 saveDVOA; - u32 saveDVOB; - u32 saveDVOC; - u32 savePP_ON; - u32 savePP_OFF; - u32 savePP_CONTROL; -- u32 savePP_CYCLE; -+ u32 savePP_DIVISOR; - u32 savePFIT_CONTROL; - u32 save_palette_a[256]; - u32 save_palette_b[256]; -@@ -189,7 +191,7 @@ typedef struct drm_i915_private { - u32 saveIMR; - u32 saveCACHE_MODE_0; - u32 saveD_STATE; -- u32 saveDSPCLK_GATE_D; -+ u32 saveCG_2D_DIS; - u32 saveMI_ARB_STATE; - u32 saveSWF0[16]; - u32 saveSWF1[16]; -@@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_device * dev, - if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ - dev_priv->ring.tail = outring; \ - dev_priv->ring.space -= outcount * 4; \ -- I915_WRITE(LP_RING + RING_TAIL, outring); \ -+ I915_WRITE(PRB0_TAIL, outring); \ - } while(0) - --extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); -- --/* Extended config space */ --#define LBB 0xf4 -- --/* VGA stuff */ -- --#define VGA_ST01_MDA 0x3ba --#define VGA_ST01_CGA 0x3da -- --#define VGA_MSR_WRITE 0x3c2 --#define VGA_MSR_READ 0x3cc --#define VGA_MSR_MEM_EN (1<<1) --#define VGA_MSR_CGA_MODE (1<<0) -- --#define VGA_SR_INDEX 0x3c4 --#define VGA_SR_DATA 0x3c5 -- --#define VGA_AR_INDEX 0x3c0 --#define VGA_AR_VID_EN (1<<5) --#define VGA_AR_DATA_WRITE 0x3c0 --#define VGA_AR_DATA_READ 0x3c1 -- --#define VGA_GR_INDEX 0x3ce --#define VGA_GR_DATA 0x3cf --/* GR05 */ --#define VGA_GR_MEM_READ_MODE_SHIFT 3 --#define VGA_GR_MEM_READ_MODE_PLANE 1 --/* GR06 */ --#define VGA_GR_MEM_MODE_MASK 0xc --#define VGA_GR_MEM_MODE_SHIFT 2 --#define VGA_GR_MEM_A0000_AFFFF 0 --#define VGA_GR_MEM_A0000_BFFFF 1 --#define VGA_GR_MEM_B0000_B7FFF 2 --#define VGA_GR_MEM_B0000_BFFFF 3 -- --#define VGA_DACMASK 0x3c6 --#define VGA_DACRX 0x3c7 --#define VGA_DACWX 0x3c8 --#define VGA_DACDATA 0x3c9 -- --#define VGA_CR_INDEX_MDA 0x3b4 --#define VGA_CR_DATA_MDA 0x3b5 --#define VGA_CR_INDEX_CGA 0x3d4 --#define VGA_CR_DATA_CGA 0x3d5 -- --#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) --#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) --#define CMD_REPORT_HEAD (7<<23) --#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) --#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) -- --#define INST_PARSER_CLIENT 0x00000000 --#define INST_OP_FLUSH 0x02000000 --#define INST_FLUSH_MAP_CACHE 0x00000001 -- --#define BB1_START_ADDR_MASK (~0x7) --#define BB1_PROTECTED (1<<0) --#define BB1_UNPROTECTED (0<<0) --#define BB2_END_ADDR_MASK (~0x7) -- --/* Framebuffer compression */ --#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ --#define FBC_LL_BASE 0x03204 /* 4k page aligned */ --#define FBC_CONTROL 0x03208 --#define FBC_CTL_EN (1<<31) --#define FBC_CTL_PERIODIC (1<<30) --#define FBC_CTL_INTERVAL_SHIFT (16) --#define FBC_CTL_UNCOMPRESSIBLE (1<<14) --#define FBC_CTL_STRIDE_SHIFT (5) --#define FBC_CTL_FENCENO (1<<0) --#define FBC_COMMAND 0x0320c --#define FBC_CMD_COMPRESS (1<<0) --#define FBC_STATUS 0x03210 --#define FBC_STAT_COMPRESSING (1<<31) --#define FBC_STAT_COMPRESSED (1<<30) --#define FBC_STAT_MODIFIED (1<<29) --#define FBC_STAT_CURRENT_LINE (1<<0) --#define FBC_CONTROL2 0x03214 --#define FBC_CTL_FENCE_DBL (0<<4) --#define FBC_CTL_IDLE_IMM (0<<2) --#define FBC_CTL_IDLE_FULL (1<<2) --#define FBC_CTL_IDLE_LINE (2<<2) --#define FBC_CTL_IDLE_DEBUG (3<<2) --#define FBC_CTL_CPU_FENCE (1<<1) --#define FBC_CTL_PLANEA (0<<0) --#define FBC_CTL_PLANEB (1<<0) --#define FBC_FENCE_OFF 0x0321b -- --#define FBC_LL_SIZE (1536) --#define FBC_LL_PAD (32) -- --/* Interrupt bits: -- */ --#define USER_INT_FLAG (1<<1) --#define VSYNC_PIPEB_FLAG (1<<5) --#define VSYNC_PIPEA_FLAG (1<<7) --#define HWB_OOM_FLAG (1<<13) /* binner out of memory */ -- --#define I915REG_HWSTAM 0x02098 --#define I915REG_INT_IDENTITY_R 0x020a4 --#define I915REG_INT_MASK_R 0x020a8 --#define I915REG_INT_ENABLE_R 0x020a0 -- --#define I915REG_PIPEASTAT 0x70024 --#define I915REG_PIPEBSTAT 0x71024 -- --#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) --#define I915_VBLANK_CLEAR (1UL<<1) -- --#define SRX_INDEX 0x3c4 --#define SRX_DATA 0x3c5 --#define SR01 1 --#define SR01_SCREEN_OFF (1<<5) -- --#define PPCR 0x61204 --#define PPCR_ON (1<<0) -- --#define DVOB 0x61140 --#define DVOB_ON (1<<31) --#define DVOC 0x61160 --#define DVOC_ON (1<<31) --#define LVDS 0x61180 --#define LVDS_ON (1<<31) -- --#define ADPA 0x61100 --#define ADPA_DPMS_MASK (~(3<<10)) --#define ADPA_DPMS_ON (0<<10) --#define ADPA_DPMS_SUSPEND (1<<10) --#define ADPA_DPMS_STANDBY (2<<10) --#define ADPA_DPMS_OFF (3<<10) -- --#define NOPID 0x2094 --#define LP_RING 0x2030 --#define HP_RING 0x2040 --/* The binner has its own ring buffer: -- */ --#define HWB_RING 0x2400 -- --#define RING_TAIL 0x00 --#define TAIL_ADDR 0x001FFFF8 --#define RING_HEAD 0x04 --#define HEAD_WRAP_COUNT 0xFFE00000 --#define HEAD_WRAP_ONE 0x00200000 --#define HEAD_ADDR 0x001FFFFC --#define RING_START 0x08 --#define START_ADDR 0x0xFFFFF000 --#define RING_LEN 0x0C --#define RING_NR_PAGES 0x001FF000 --#define RING_REPORT_MASK 0x00000006 --#define RING_REPORT_64K 0x00000002 --#define RING_REPORT_128K 0x00000004 --#define RING_NO_REPORT 0x00000000 --#define RING_VALID_MASK 0x00000001 --#define RING_VALID 0x00000001 --#define RING_INVALID 0x00000000 -- --/* Instruction parser error reg: -- */ --#define IPEIR 0x2088 -- --/* Scratch pad debug 0 reg: -- */ --#define SCPD0 0x209c -- --/* Error status reg: -- */ --#define ESR 0x20b8 -- --/* Secondary DMA fetch address debug reg: -- */ --#define DMA_FADD_S 0x20d4 -- --/* Memory Interface Arbitration State -- */ --#define MI_ARB_STATE 0x20e4 -- --/* Cache mode 0 reg. -- * - Manipulating render cache behaviour is central -- * to the concept of zone rendering, tuning this reg can help avoid -- * unnecessary render cache reads and even writes (for z/stencil) -- * at beginning and end of scene. -- * -- * - To change a bit, write to this reg with a mask bit set and the -- * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. -- */ --#define Cache_Mode_0 0x2120 --#define CACHE_MODE_0 0x2120 --#define CM0_MASK_SHIFT 16 --#define CM0_IZ_OPT_DISABLE (1<<6) --#define CM0_ZR_OPT_DISABLE (1<<5) --#define CM0_DEPTH_EVICT_DISABLE (1<<4) --#define CM0_COLOR_EVICT_DISABLE (1<<3) --#define CM0_DEPTH_WRITE_DISABLE (1<<1) --#define CM0_RC_OP_FLUSH_DISABLE (1<<0) -- -- --/* Graphics flush control. A CPU write flushes the GWB of all writes. -- * The data is discarded. -- */ --#define GFX_FLSH_CNTL 0x2170 -- --/* Binner control. Defines the location of the bin pointer list: -- */ --#define BINCTL 0x2420 --#define BC_MASK (1 << 9) -- --/* Binned scene info. -- */ --#define BINSCENE 0x2428 --#define BS_OP_LOAD (1 << 8) --#define BS_MASK (1 << 22) -- --/* Bin command parser debug reg: -- */ --#define BCPD 0x2480 -- --/* Bin memory control debug reg: -- */ --#define BMCD 0x2484 -- --/* Bin data cache debug reg: -- */ --#define BDCD 0x2488 -- --/* Binner pointer cache debug reg: -- */ --#define BPCD 0x248c -- --/* Binner scratch pad debug reg: -- */ --#define BINSKPD 0x24f0 -- --/* HWB scratch pad debug reg: -- */ --#define HWBSKPD 0x24f4 -- --/* Binner memory pool reg: -- */ --#define BMP_BUFFER 0x2430 --#define BMP_PAGE_SIZE_4K (0 << 10) --#define BMP_BUFFER_SIZE_SHIFT 1 --#define BMP_ENABLE (1 << 0) -- --/* Get/put memory from the binner memory pool: -- */ --#define BMP_GET 0x2438 --#define BMP_PUT 0x2440 --#define BMP_OFFSET_SHIFT 5 -- --/* 3D state packets: -- */ --#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -- --#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) --#define SC_UPDATE_SCISSOR (0x1<<1) --#define SC_ENABLE_MASK (0x1<<0) --#define SC_ENABLE (0x1<<0) -- --#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) -- --#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) --#define SCI_YMIN_MASK (0xffff<<16) --#define SCI_XMIN_MASK (0xffff<<0) --#define SCI_YMAX_MASK (0xffff<<16) --#define SCI_XMAX_MASK (0xffff<<0) -- --#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) --#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) --#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) --#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) --#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) --#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) --#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) -- --#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -- --#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) --#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) --#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) --#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) --#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) --#define XY_SRC_COPY_BLT_DST_TILED (1<<11) -- --#define MI_BATCH_BUFFER ((0x30<<23)|1) --#define MI_BATCH_BUFFER_START (0x31<<23) --#define MI_BATCH_BUFFER_END (0xA<<23) --#define MI_BATCH_NON_SECURE (1) --#define MI_BATCH_NON_SECURE_I965 (1<<8) -- --#define MI_WAIT_FOR_EVENT ((0x3<<23)) --#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) --#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) --#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) -- --#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) -- --#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) --#define ASYNC_FLIP (1<<22) --#define DISPLAY_PLANE_A (0<<20) --#define DISPLAY_PLANE_B (1<<20) -- --/* Display regs */ --#define DSPACNTR 0x70180 --#define DSPBCNTR 0x71180 --#define DISPPLANE_SEL_PIPE_MASK (1<<24) -- --/* Define the region of interest for the binner: -- */ --#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) -- --#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -- --#define CMD_MI_FLUSH (0x04 << 23) --#define MI_NO_WRITE_FLUSH (1 << 2) --#define MI_READ_FLUSH (1 << 0) --#define MI_EXE_FLUSH (1 << 1) --#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ --#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -- --#define BREADCRUMB_BITS 31 --#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) -- --#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) --#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) -- --#define BLC_PWM_CTL 0x61254 --#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) -- --#define BLC_PWM_CTL2 0x61250 - /** -- * This is the most significant 15 bits of the number of backlight cycles in a -- * complete cycle of the modulated backlight control. -+ * Reads a dword out of the status page, which is written to from the command -+ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or -+ * MI_STORE_DATA_IMM. - * -- * The actual value is this field multiplied by two. -- */ --#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) --#define BLM_LEGACY_MODE (1 << 16) --/** -- * This is the number of cycles out of the backlight modulation cycle for which -- * the backlight is on. -+ * The following dwords have a reserved meaning: -+ * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes. -+ * 4: ring 0 head pointer -+ * 5: ring 1 head pointer (915-class) -+ * 6: ring 2 head pointer (915-class) - * -- * This field must be no greater than the number of cycles in the complete -- * backlight modulation cycle. -- */ --#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) --#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) -- --#define I915_GCFGC 0xf0 --#define I915_LOW_FREQUENCY_ENABLE (1 << 7) --#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) --#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) --#define I915_DISPLAY_CLOCK_MASK (7 << 4) -- --#define I855_HPLLCC 0xc0 --#define I855_CLOCK_CONTROL_MASK (3 << 0) --#define I855_CLOCK_133_200 (0 << 0) --#define I855_CLOCK_100_200 (1 << 0) --#define I855_CLOCK_100_133 (2 << 0) --#define I855_CLOCK_166_250 (3 << 0) -- --/* p317, 319 -+ * The area from dword 0x10 to 0x3ff is available for driver usage. - */ --#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ --#define VCLK2_VCO_N 0x600a --#define VCLK2_VCO_DIV_SEL 0x6012 -- --#define VCLK_DIVISOR_VGA0 0x6000 --#define VCLK_DIVISOR_VGA1 0x6004 --#define VCLK_POST_DIV 0x6010 --/** Selects a post divisor of 4 instead of 2. */ --# define VGA1_PD_P2_DIV_4 (1 << 15) --/** Overrides the p2 post divisor field */ --# define VGA1_PD_P1_DIV_2 (1 << 13) --# define VGA1_PD_P1_SHIFT 8 --/** P1 value is 2 greater than this field */ --# define VGA1_PD_P1_MASK (0x1f << 8) --/** Selects a post divisor of 4 instead of 2. */ --# define VGA0_PD_P2_DIV_4 (1 << 7) --/** Overrides the p2 post divisor field */ --# define VGA0_PD_P1_DIV_2 (1 << 5) --# define VGA0_PD_P1_SHIFT 0 --/** P1 value is 2 greater than this field */ --# define VGA0_PD_P1_MASK (0x1f << 0) -- --/* PCI D state control register */ --#define D_STATE 0x6104 --#define DSPCLK_GATE_D 0x6200 -- --/* I830 CRTC registers */ --#define HTOTAL_A 0x60000 --#define HBLANK_A 0x60004 --#define HSYNC_A 0x60008 --#define VTOTAL_A 0x6000c --#define VBLANK_A 0x60010 --#define VSYNC_A 0x60014 --#define PIPEASRC 0x6001c --#define BCLRPAT_A 0x60020 --#define VSYNCSHIFT_A 0x60028 -- --#define HTOTAL_B 0x61000 --#define HBLANK_B 0x61004 --#define HSYNC_B 0x61008 --#define VTOTAL_B 0x6100c --#define VBLANK_B 0x61010 --#define VSYNC_B 0x61014 --#define PIPEBSRC 0x6101c --#define BCLRPAT_B 0x61020 --#define VSYNCSHIFT_B 0x61028 -- --#define PP_STATUS 0x61200 --# define PP_ON (1 << 31) --/** -- * Indicates that all dependencies of the panel are on: -- * -- * - PLL enabled -- * - pipe enabled -- * - LVDS/DVOB/DVOC on -- */ --# define PP_READY (1 << 30) --# define PP_SEQUENCE_NONE (0 << 28) --# define PP_SEQUENCE_ON (1 << 28) --# define PP_SEQUENCE_OFF (2 << 28) --# define PP_SEQUENCE_MASK 0x30000000 --#define PP_CONTROL 0x61204 --# define POWER_TARGET_ON (1 << 0) -- --#define LVDSPP_ON 0x61208 --#define LVDSPP_OFF 0x6120c --#define PP_CYCLE 0x61210 -- --#define PFIT_CONTROL 0x61230 --# define PFIT_ENABLE (1 << 31) --# define PFIT_PIPE_MASK (3 << 29) --# define PFIT_PIPE_SHIFT 29 --# define VERT_INTERP_DISABLE (0 << 10) --# define VERT_INTERP_BILINEAR (1 << 10) --# define VERT_INTERP_MASK (3 << 10) --# define VERT_AUTO_SCALE (1 << 9) --# define HORIZ_INTERP_DISABLE (0 << 6) --# define HORIZ_INTERP_BILINEAR (1 << 6) --# define HORIZ_INTERP_MASK (3 << 6) --# define HORIZ_AUTO_SCALE (1 << 5) --# define PANEL_8TO6_DITHER_ENABLE (1 << 3) -- --#define PFIT_PGM_RATIOS 0x61234 --# define PFIT_VERT_SCALE_MASK 0xfff00000 --# define PFIT_HORIZ_SCALE_MASK 0x0000fff0 -- --#define PFIT_AUTO_RATIOS 0x61238 -- -- --#define DPLL_A 0x06014 --#define DPLL_B 0x06018 --# define DPLL_VCO_ENABLE (1 << 31) --# define DPLL_DVO_HIGH_SPEED (1 << 30) --# define DPLL_SYNCLOCK_ENABLE (1 << 29) --# define DPLL_VGA_MODE_DIS (1 << 28) --# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ --# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ --# define DPLL_MODE_MASK (3 << 26) --# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ --# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ --# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ --# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ --# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ --# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ --/** -- * The i830 generation, in DAC/serial mode, defines p1 as two plus this -- * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. -- */ --# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 --/** -- * The i830 generation, in LVDS mode, defines P1 as the bit number set within -- * this field (only one bit may be set). -- */ --# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 --# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 --# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ --# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ --# define PLL_REF_INPUT_DREFCLK (0 << 13) --# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ --# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ --# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) --# define PLL_REF_INPUT_MASK (3 << 13) --# define PLL_LOAD_PULSE_PHASE_SHIFT 9 --/* -- * Parallel to Serial Load Pulse phase selection. -- * Selects the phase for the 10X DPLL clock for the PCIe -- * digital display port. The range is 4 to 13; 10 or more -- * is just a flip delay. The default is 6 -- */ --# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) --# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) -- --/** -- * SDVO multiplier for 945G/GM. Not used on 965. -- * -- * \sa DPLL_MD_UDI_MULTIPLIER_MASK -- */ --# define SDVO_MULTIPLIER_MASK 0x000000ff --# define SDVO_MULTIPLIER_SHIFT_HIRES 4 --# define SDVO_MULTIPLIER_SHIFT_VGA 0 -- --/** @defgroup DPLL_MD -- * @{ -- */ --/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ --#define DPLL_A_MD 0x0601c --/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ --#define DPLL_B_MD 0x06020 --/** -- * UDI pixel divider, controlling how many pixels are stuffed into a packet. -- * -- * Value is pixels minus 1. Must be set to 1 pixel for SDVO. -- */ --# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 --# define DPLL_MD_UDI_DIVIDER_SHIFT 24 --/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ --# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 --# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 --/** -- * SDVO/UDI pixel multiplier. -- * -- * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus -- * clock rate is 10 times the DPLL clock. At low resolution/refresh rate -- * modes, the bus rate would be below the limits, so SDVO allows for stuffing -- * dummy bytes in the datastream at an increased clock rate, with both sides of -- * the link knowing how many bytes are fill. -- * -- * So, for a mode with a dotclock of 65Mhz, we would want to double the clock -- * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be -- * set to 130Mhz, and the SDVO multiplier set to 2x in this register and -- * through an SDVO command. -- * -- * This register field has values of multiplication factor minus 1, with -- * a maximum multiplier of 5 for SDVO. -- */ --# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 --# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 --/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. -- * This best be set to the default value (3) or the CRT won't work. No, -- * I don't entirely understand what this does... -- */ --# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f --# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 --/** @} */ -- --#define DPLL_TEST 0x606c --# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) --# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) --# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) --# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) --# define DPLLB_TEST_N_BYPASS (1 << 19) --# define DPLLB_TEST_M_BYPASS (1 << 18) --# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) --# define DPLLA_TEST_N_BYPASS (1 << 3) --# define DPLLA_TEST_M_BYPASS (1 << 2) --# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) -- --#define ADPA 0x61100 --#define ADPA_DAC_ENABLE (1<<31) --#define ADPA_DAC_DISABLE 0 --#define ADPA_PIPE_SELECT_MASK (1<<30) --#define ADPA_PIPE_A_SELECT 0 --#define ADPA_PIPE_B_SELECT (1<<30) --#define ADPA_USE_VGA_HVPOLARITY (1<<15) --#define ADPA_SETS_HVPOLARITY 0 --#define ADPA_VSYNC_CNTL_DISABLE (1<<11) --#define ADPA_VSYNC_CNTL_ENABLE 0 --#define ADPA_HSYNC_CNTL_DISABLE (1<<10) --#define ADPA_HSYNC_CNTL_ENABLE 0 --#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) --#define ADPA_VSYNC_ACTIVE_LOW 0 --#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) --#define ADPA_HSYNC_ACTIVE_LOW 0 -- --#define FPA0 0x06040 --#define FPA1 0x06044 --#define FPB0 0x06048 --#define FPB1 0x0604c --# define FP_N_DIV_MASK 0x003f0000 --# define FP_N_DIV_SHIFT 16 --# define FP_M1_DIV_MASK 0x00003f00 --# define FP_M1_DIV_SHIFT 8 --# define FP_M2_DIV_MASK 0x0000003f --# define FP_M2_DIV_SHIFT 0 -- -- --#define PORT_HOTPLUG_EN 0x61110 --# define SDVOB_HOTPLUG_INT_EN (1 << 26) --# define SDVOC_HOTPLUG_INT_EN (1 << 25) --# define TV_HOTPLUG_INT_EN (1 << 18) --# define CRT_HOTPLUG_INT_EN (1 << 9) --# define CRT_HOTPLUG_FORCE_DETECT (1 << 3) -- --#define PORT_HOTPLUG_STAT 0x61114 --# define CRT_HOTPLUG_INT_STATUS (1 << 11) --# define TV_HOTPLUG_INT_STATUS (1 << 10) --# define CRT_HOTPLUG_MONITOR_MASK (3 << 8) --# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) --# define CRT_HOTPLUG_MONITOR_MONO (2 << 8) --# define CRT_HOTPLUG_MONITOR_NONE (0 << 8) --# define SDVOC_HOTPLUG_INT_STATUS (1 << 7) --# define SDVOB_HOTPLUG_INT_STATUS (1 << 6) -- --#define SDVOB 0x61140 --#define SDVOC 0x61160 --#define SDVO_ENABLE (1 << 31) --#define SDVO_PIPE_B_SELECT (1 << 30) --#define SDVO_STALL_SELECT (1 << 29) --#define SDVO_INTERRUPT_ENABLE (1 << 26) --/** -- * 915G/GM SDVO pixel multiplier. -- * -- * Programmed value is multiplier - 1, up to 5x. -- * -- * \sa DPLL_MD_UDI_MULTIPLIER_MASK -- */ --#define SDVO_PORT_MULTIPLY_MASK (7 << 23) --#define SDVO_PORT_MULTIPLY_SHIFT 23 --#define SDVO_PHASE_SELECT_MASK (15 << 19) --#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) --#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) --#define SDVOC_GANG_MODE (1 << 16) --#define SDVO_BORDER_ENABLE (1 << 7) --#define SDVOB_PCIE_CONCURRENCY (1 << 3) --#define SDVO_DETECTED (1 << 2) --/* Bits to be preserved when writing */ --#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) --#define SDVOC_PRESERVE_MASK (1 << 17) -- --/** @defgroup LVDS -- * @{ -- */ --/** -- * This register controls the LVDS output enable, pipe selection, and data -- * format selection. -- * -- * All of the clock/data pairs are force powered down by power sequencing. -- */ --#define LVDS 0x61180 --/** -- * Enables the LVDS port. This bit must be set before DPLLs are enabled, as -- * the DPLL semantics change when the LVDS is assigned to that pipe. -- */ --# define LVDS_PORT_EN (1 << 31) --/** Selects pipe B for LVDS data. Must be set on pre-965. */ --# define LVDS_PIPEB_SELECT (1 << 30) -- --/** -- * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per -- * pixel. -- */ --# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) --# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) --# define LVDS_A0A2_CLKA_POWER_UP (3 << 8) --/** -- * Controls the A3 data pair, which contains the additional LSBs for 24 bit -- * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be -- * on. -- */ --# define LVDS_A3_POWER_MASK (3 << 6) --# define LVDS_A3_POWER_DOWN (0 << 6) --# define LVDS_A3_POWER_UP (3 << 6) --/** -- * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP -- * is set. -- */ --# define LVDS_CLKB_POWER_MASK (3 << 4) --# define LVDS_CLKB_POWER_DOWN (0 << 4) --# define LVDS_CLKB_POWER_UP (3 << 4) -- --/** -- * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 -- * setting for whether we are in dual-channel mode. The B3 pair will -- * additionally only be powered up when LVDS_A3_POWER_UP is set. -- */ --# define LVDS_B0B3_POWER_MASK (3 << 2) --# define LVDS_B0B3_POWER_DOWN (0 << 2) --# define LVDS_B0B3_POWER_UP (3 << 2) -- --#define PIPEACONF 0x70008 --#define PIPEACONF_ENABLE (1<<31) --#define PIPEACONF_DISABLE 0 --#define PIPEACONF_DOUBLE_WIDE (1<<30) --#define I965_PIPECONF_ACTIVE (1<<30) --#define PIPEACONF_SINGLE_WIDE 0 --#define PIPEACONF_PIPE_UNLOCKED 0 --#define PIPEACONF_PIPE_LOCKED (1<<25) --#define PIPEACONF_PALETTE 0 --#define PIPEACONF_GAMMA (1<<24) --#define PIPECONF_FORCE_BORDER (1<<25) --#define PIPECONF_PROGRESSIVE (0 << 21) --#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) --#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) -- --#define DSPARB 0x70030 --#define DSPARB_CSTART_MASK (0x7f << 7) --#define DSPARB_CSTART_SHIFT 7 --#define DSPARB_BSTART_MASK (0x7f) --#define DSPARB_BSTART_SHIFT 0 -- --#define PIPEBCONF 0x71008 --#define PIPEBCONF_ENABLE (1<<31) --#define PIPEBCONF_DISABLE 0 --#define PIPEBCONF_DOUBLE_WIDE (1<<30) --#define PIPEBCONF_DISABLE 0 --#define PIPEBCONF_GAMMA (1<<24) --#define PIPEBCONF_PALETTE 0 -- --#define PIPEBGCMAXRED 0x71010 --#define PIPEBGCMAXGREEN 0x71014 --#define PIPEBGCMAXBLUE 0x71018 --#define PIPEBSTAT 0x71024 --#define PIPEBFRAMEHIGH 0x71040 --#define PIPEBFRAMEPIXEL 0x71044 -- --#define DSPACNTR 0x70180 --#define DSPBCNTR 0x71180 --#define DISPLAY_PLANE_ENABLE (1<<31) --#define DISPLAY_PLANE_DISABLE 0 --#define DISPPLANE_GAMMA_ENABLE (1<<30) --#define DISPPLANE_GAMMA_DISABLE 0 --#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) --#define DISPPLANE_8BPP (0x2<<26) --#define DISPPLANE_15_16BPP (0x4<<26) --#define DISPPLANE_16BPP (0x5<<26) --#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) --#define DISPPLANE_32BPP (0x7<<26) --#define DISPPLANE_STEREO_ENABLE (1<<25) --#define DISPPLANE_STEREO_DISABLE 0 --#define DISPPLANE_SEL_PIPE_MASK (1<<24) --#define DISPPLANE_SEL_PIPE_A 0 --#define DISPPLANE_SEL_PIPE_B (1<<24) --#define DISPPLANE_SRC_KEY_ENABLE (1<<22) --#define DISPPLANE_SRC_KEY_DISABLE 0 --#define DISPPLANE_LINE_DOUBLE (1<<20) --#define DISPPLANE_NO_LINE_DOUBLE 0 --#define DISPPLANE_STEREO_POLARITY_FIRST 0 --#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) --/* plane B only */ --#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) --#define DISPPLANE_ALPHA_TRANS_DISABLE 0 --#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 --#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -- --#define DSPABASE 0x70184 --#define DSPASTRIDE 0x70188 -- --#define DSPBBASE 0x71184 --#define DSPBADDR DSPBBASE --#define DSPBSTRIDE 0x71188 -- --#define DSPAKEYVAL 0x70194 --#define DSPAKEYMASK 0x70198 -- --#define DSPAPOS 0x7018C /* reserved */ --#define DSPASIZE 0x70190 --#define DSPBPOS 0x7118C --#define DSPBSIZE 0x71190 -- --#define DSPASURF 0x7019C --#define DSPATILEOFF 0x701A4 -- --#define DSPBSURF 0x7119C --#define DSPBTILEOFF 0x711A4 -- --#define VGACNTRL 0x71400 --# define VGA_DISP_DISABLE (1 << 31) --# define VGA_2X_MODE (1 << 30) --# define VGA_PIPE_B_SELECT (1 << 29) -- --/* -- * Some BIOS scratch area registers. The 845 (and 830?) store the amount -- * of video memory available to the BIOS in SWF1. -- */ -- --#define SWF0 0x71410 -- --/* -- * 855 scratch registers. -- */ --#define SWF10 0x70410 -- --#define SWF30 0x72414 -- --/* -- * Overlay registers. These are overlay registers accessed via MMIO. -- * Those loaded via the overlay register page are defined in i830_video.c. -- */ --#define OVADD 0x30000 -- --#define DOVSTA 0x30008 --#define OC_BUF (0x3<<20) -+#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) -+#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5) - --#define OGAMC5 0x30010 --#define OGAMC4 0x30014 --#define OGAMC3 0x30018 --#define OGAMC2 0x3001c --#define OGAMC1 0x30020 --#define OGAMC0 0x30024 --/* -- * Palette registers -- */ --#define PALETTE_A 0x0a000 --#define PALETTE_B 0x0a800 -+extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); - - #define IS_I830(dev) ((dev)->pci_device == 0x3577) - #define IS_845G(dev) ((dev)->pci_device == 0x2562) -diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c -index df03611..4a2de78 100644 ---- a/drivers/gpu/drm/i915/i915_irq.c -+++ b/drivers/gpu/drm/i915/i915_irq.c -@@ -31,10 +31,6 @@ - #include "i915_drm.h" - #include "i915_drv.h" - --#define USER_INT_FLAG (1<<1) --#define VSYNC_PIPEB_FLAG (1<<5) --#define VSYNC_PIPEA_FLAG (1<<7) -- - #define MAX_NOPID ((u32)~0) - - /** -@@ -236,40 +232,43 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) - u16 temp; - u32 pipea_stats, pipeb_stats; - -- pipea_stats = I915_READ(I915REG_PIPEASTAT); -- pipeb_stats = I915_READ(I915REG_PIPEBSTAT); -+ pipea_stats = I915_READ(PIPEASTAT); -+ pipeb_stats = I915_READ(PIPEBSTAT); - -- temp = I915_READ16(I915REG_INT_IDENTITY_R); -+ temp = I915_READ16(IIR); - -- temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG); -+ temp &= (I915_USER_INTERRUPT | -+ I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | -+ I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT); - - DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); - - if (temp == 0) - return IRQ_NONE; - -- I915_WRITE16(I915REG_INT_IDENTITY_R, temp); -- (void) I915_READ16(I915REG_INT_IDENTITY_R); -+ I915_WRITE16(IIR, temp); -+ (void) I915_READ16(IIR); - DRM_READMEMORYBARRIER(); - - dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); - -- if (temp & USER_INT_FLAG) -+ if (temp & I915_USER_INTERRUPT) - DRM_WAKEUP(&dev_priv->irq_queue); - -- if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) { -+ if (temp & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | -+ I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) { - int vblank_pipe = dev_priv->vblank_pipe; - - if ((vblank_pipe & - (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) - == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) { -- if (temp & VSYNC_PIPEA_FLAG) -+ if (temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) - atomic_inc(&dev->vbl_received); -- if (temp & VSYNC_PIPEB_FLAG) -+ if (temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) - atomic_inc(&dev->vbl_received2); -- } else if (((temp & VSYNC_PIPEA_FLAG) && -+ } else if (((temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) && - (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) || -- ((temp & VSYNC_PIPEB_FLAG) && -+ ((temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) && - (vblank_pipe & DRM_I915_VBLANK_PIPE_B))) - atomic_inc(&dev->vbl_received); - -@@ -278,12 +277,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) - - if (dev_priv->swaps_pending > 0) - drm_locked_tasklet(dev, i915_vblank_tasklet); -- I915_WRITE(I915REG_PIPEASTAT, -+ I915_WRITE(PIPEASTAT, - pipea_stats|I915_VBLANK_INTERRUPT_ENABLE| -- I915_VBLANK_CLEAR); -- I915_WRITE(I915REG_PIPEBSTAT, -+ PIPE_VBLANK_INTERRUPT_STATUS); -+ I915_WRITE(PIPEBSTAT, - pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE| -- I915_VBLANK_CLEAR); -+ PIPE_VBLANK_INTERRUPT_STATUS); - } - - return IRQ_HANDLED; -@@ -304,12 +303,12 @@ static int i915_emit_irq(struct drm_device * dev) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; - - BEGIN_LP_RING(6); -- OUT_RING(CMD_STORE_DWORD_IDX); -- OUT_RING(20); -+ OUT_RING(MI_STORE_DWORD_INDEX); -+ OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(0); - OUT_RING(0); -- OUT_RING(GFX_OP_USER_INTERRUPT); -+ OUT_RING(MI_USER_INTERRUPT); - ADVANCE_LP_RING(); - - return dev_priv->counter; -@@ -421,11 +420,11 @@ static void i915_enable_interrupt (struct drm_device *dev) - - flag = 0; - if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A) -- flag |= VSYNC_PIPEA_FLAG; -+ flag |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; - if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B) -- flag |= VSYNC_PIPEB_FLAG; -+ flag |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; - -- I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag); -+ I915_WRITE16(IER, I915_USER_INTERRUPT | flag); - } - - /* Set the vblank monitor pipe -@@ -465,11 +464,11 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data, - return -EINVAL; - } - -- flag = I915_READ(I915REG_INT_ENABLE_R); -+ flag = I915_READ(IER); - pipe->pipe = 0; -- if (flag & VSYNC_PIPEA_FLAG) -+ if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) - pipe->pipe |= DRM_I915_VBLANK_PIPE_A; -- if (flag & VSYNC_PIPEB_FLAG) -+ if (flag & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) - pipe->pipe |= DRM_I915_VBLANK_PIPE_B; - - return 0; -@@ -587,9 +586,9 @@ void i915_driver_irq_preinstall(struct drm_device * dev) - { - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - -- I915_WRITE16(I915REG_HWSTAM, 0xfffe); -- I915_WRITE16(I915REG_INT_MASK_R, 0x0); -- I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); -+ I915_WRITE16(HWSTAM, 0xfffe); -+ I915_WRITE16(IMR, 0x0); -+ I915_WRITE16(IER, 0x0); - } - - void i915_driver_irq_postinstall(struct drm_device * dev) -@@ -614,10 +613,10 @@ void i915_driver_irq_uninstall(struct drm_device * dev) - if (!dev_priv) - return; - -- I915_WRITE16(I915REG_HWSTAM, 0xffff); -- I915_WRITE16(I915REG_INT_MASK_R, 0xffff); -- I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); -+ I915_WRITE16(HWSTAM, 0xffff); -+ I915_WRITE16(IMR, 0xffff); -+ I915_WRITE16(IER, 0x0); - -- temp = I915_READ16(I915REG_INT_IDENTITY_R); -- I915_WRITE16(I915REG_INT_IDENTITY_R, temp); -+ temp = I915_READ16(IIR); -+ I915_WRITE16(IIR, temp); - } -diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h -new file mode 100644 -index 0000000..477c64e ---- /dev/null -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -0,0 +1,1405 @@ -+/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the -+ * "Software"), to deal in the Software without restriction, including -+ * without limitation the rights to use, copy, modify, merge, publish, -+ * distribute, sub license, and/or sell copies of the Software, and to -+ * permit persons to whom the Software is furnished to do so, subject to -+ * the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the -+ * next paragraph) shall be included in all copies or substantial portions -+ * of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR -+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef _I915_REG_H_ -+#define _I915_REG_H_ -+ -+/* MCH MMIO space */ -+/** 915-945 and GM965 MCH register controlling DRAM channel access */ -+#define DCC 0x200 -+#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) -+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) -+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) -+#define DCC_ADDRESSING_MODE_MASK (3 << 0) -+#define DCC_CHANNEL_XOR_DISABLE (1 << 10) -+ -+/** 965 MCH register controlling DRAM channel configuration */ -+#define CHDECMISC 0x111 -+#define CHDECMISC_FLEXMEMORY (1 << 1) -+ -+/* -+ * The Bridge device's PCI config space has information about the -+ * fb aperture size and the amount of pre-reserved memory. -+ */ -+#define INTEL_GMCH_CTRL 0x52 -+#define INTEL_GMCH_ENABLED 0x4 -+#define INTEL_GMCH_MEM_MASK 0x1 -+#define INTEL_GMCH_MEM_64M 0x1 -+#define INTEL_GMCH_MEM_128M 0 -+ -+#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) -+#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) -+#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) -+#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) -+#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) -+#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) -+#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) -+ -+#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) -+#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) -+ -+/* PCI config space */ -+ -+#define HPLLCC 0xc0 /* 855 only */ -+#define GC_CLOCK_CONTROL_MASK (3 << 0) -+#define GC_CLOCK_133_200 (0 << 0) -+#define GC_CLOCK_100_200 (1 << 0) -+#define GC_CLOCK_100_133 (2 << 0) -+#define GC_CLOCK_166_250 (3 << 0) -+#define GCFGC 0xf0 /* 915+ only */ -+#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -+#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -+#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -+#define GC_DISPLAY_CLOCK_MASK (7 << 4) -+#define LBB 0xf4 -+ -+/* VGA stuff */ -+ -+#define VGA_ST01_MDA 0x3ba -+#define VGA_ST01_CGA 0x3da -+ -+#define VGA_MSR_WRITE 0x3c2 -+#define VGA_MSR_READ 0x3cc -+#define VGA_MSR_MEM_EN (1<<1) -+#define VGA_MSR_CGA_MODE (1<<0) -+ -+#define VGA_SR_INDEX 0x3c4 -+#define VGA_SR_DATA 0x3c5 -+ -+#define VGA_AR_INDEX 0x3c0 -+#define VGA_AR_VID_EN (1<<5) -+#define VGA_AR_DATA_WRITE 0x3c0 -+#define VGA_AR_DATA_READ 0x3c1 -+ -+#define VGA_GR_INDEX 0x3ce -+#define VGA_GR_DATA 0x3cf -+/* GR05 */ -+#define VGA_GR_MEM_READ_MODE_SHIFT 3 -+#define VGA_GR_MEM_READ_MODE_PLANE 1 -+/* GR06 */ -+#define VGA_GR_MEM_MODE_MASK 0xc -+#define VGA_GR_MEM_MODE_SHIFT 2 -+#define VGA_GR_MEM_A0000_AFFFF 0 -+#define VGA_GR_MEM_A0000_BFFFF 1 -+#define VGA_GR_MEM_B0000_B7FFF 2 -+#define VGA_GR_MEM_B0000_BFFFF 3 -+ -+#define VGA_DACMASK 0x3c6 -+#define VGA_DACRX 0x3c7 -+#define VGA_DACWX 0x3c8 -+#define VGA_DACDATA 0x3c9 -+ -+#define VGA_CR_INDEX_MDA 0x3b4 -+#define VGA_CR_DATA_MDA 0x3b5 -+#define VGA_CR_INDEX_CGA 0x3d4 -+#define VGA_CR_DATA_CGA 0x3d5 -+ -+/* -+ * Memory interface instructions used by the kernel -+ */ -+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) -+ -+#define MI_NOOP MI_INSTR(0, 0) -+#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -+#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -+#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -+#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) -+#define MI_FLUSH MI_INSTR(0x04, 0) -+#define MI_READ_FLUSH (1 << 0) -+#define MI_EXE_FLUSH (1 << 1) -+#define MI_NO_WRITE_FLUSH (1 << 2) -+#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -+#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -+#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) -+#define MI_REPORT_HEAD MI_INSTR(0x07, 0) -+#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) -+#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -+#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ -+#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -+#define MI_STORE_DWORD_INDEX_SHIFT 2 -+#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) -+#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -+#define MI_BATCH_NON_SECURE (1) -+#define MI_BATCH_NON_SECURE_I965 (1<<8) -+#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) -+ -+/* -+ * 3D instructions used by the kernel -+ */ -+#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) -+ -+#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -+#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -+#define SC_UPDATE_SCISSOR (0x1<<1) -+#define SC_ENABLE_MASK (0x1<<0) -+#define SC_ENABLE (0x1<<0) -+#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) -+#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -+#define SCI_YMIN_MASK (0xffff<<16) -+#define SCI_XMIN_MASK (0xffff<<0) -+#define SCI_YMAX_MASK (0xffff<<16) -+#define SCI_XMAX_MASK (0xffff<<0) -+#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -+#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -+#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -+#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -+#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -+#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) -+#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -+#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) -+#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -+#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) -+#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -+#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) -+#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -+#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -+#define BLT_DEPTH_8 (0<<24) -+#define BLT_DEPTH_16_565 (1<<24) -+#define BLT_DEPTH_16_1555 (2<<24) -+#define BLT_DEPTH_32 (3<<24) -+#define BLT_ROP_GXCOPY (0xcc<<16) -+#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ -+#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ -+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -+#define ASYNC_FLIP (1<<22) -+#define DISPLAY_PLANE_A (0<<20) -+#define DISPLAY_PLANE_B (1<<20) -+ -+/* -+ * Instruction and interrupt control regs -+ */ -+ -+#define PRB0_TAIL 0x02030 -+#define PRB0_HEAD 0x02034 -+#define PRB0_START 0x02038 -+#define PRB0_CTL 0x0203c -+#define TAIL_ADDR 0x001FFFF8 -+#define HEAD_WRAP_COUNT 0xFFE00000 -+#define HEAD_WRAP_ONE 0x00200000 -+#define HEAD_ADDR 0x001FFFFC -+#define RING_NR_PAGES 0x001FF000 -+#define RING_REPORT_MASK 0x00000006 -+#define RING_REPORT_64K 0x00000002 -+#define RING_REPORT_128K 0x00000004 -+#define RING_NO_REPORT 0x00000000 -+#define RING_VALID_MASK 0x00000001 -+#define RING_VALID 0x00000001 -+#define RING_INVALID 0x00000000 -+#define PRB1_TAIL 0x02040 /* 915+ only */ -+#define PRB1_HEAD 0x02044 /* 915+ only */ -+#define PRB1_START 0x02048 /* 915+ only */ -+#define PRB1_CTL 0x0204c /* 915+ only */ -+#define ACTHD_I965 0x02074 -+#define HWS_PGA 0x02080 -+#define HWS_ADDRESS_MASK 0xfffff000 -+#define HWS_START_ADDRESS_SHIFT 4 -+#define IPEIR 0x02088 -+#define NOPID 0x02094 -+#define HWSTAM 0x02098 -+#define SCPD0 0x0209c /* 915+ only */ -+#define IER 0x020a0 -+#define IIR 0x020a4 -+#define IMR 0x020a8 -+#define ISR 0x020ac -+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -+#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -+#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) -+#define I915_HWB_OOM_INTERRUPT (1<<13) -+#define I915_SYNC_STATUS_INTERRUPT (1<<12) -+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -+#define I915_DEBUG_INTERRUPT (1<<2) -+#define I915_USER_INTERRUPT (1<<1) -+#define I915_ASLE_INTERRUPT (1<<0) -+#define EIR 0x020b0 -+#define EMR 0x020b4 -+#define ESR 0x020b8 -+#define INSTPM 0x020c0 -+#define ACTHD 0x020c8 -+#define FW_BLC 0x020d8 -+#define FW_BLC_SELF 0x020e0 /* 915+ only */ -+#define MI_ARB_STATE 0x020e4 /* 915+ only */ -+#define CACHE_MODE_0 0x02120 /* 915+ only */ -+#define CM0_MASK_SHIFT 16 -+#define CM0_IZ_OPT_DISABLE (1<<6) -+#define CM0_ZR_OPT_DISABLE (1<<5) -+#define CM0_DEPTH_EVICT_DISABLE (1<<4) -+#define CM0_COLOR_EVICT_DISABLE (1<<3) -+#define CM0_DEPTH_WRITE_DISABLE (1<<1) -+#define CM0_RC_OP_FLUSH_DISABLE (1<<0) -+#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ -+ -+/* -+ * Framebuffer compression (915+ only) -+ */ -+ -+#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ -+#define FBC_LL_BASE 0x03204 /* 4k page aligned */ -+#define FBC_CONTROL 0x03208 -+#define FBC_CTL_EN (1<<31) -+#define FBC_CTL_PERIODIC (1<<30) -+#define FBC_CTL_INTERVAL_SHIFT (16) -+#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -+#define FBC_CTL_STRIDE_SHIFT (5) -+#define FBC_CTL_FENCENO (1<<0) -+#define FBC_COMMAND 0x0320c -+#define FBC_CMD_COMPRESS (1<<0) -+#define FBC_STATUS 0x03210 -+#define FBC_STAT_COMPRESSING (1<<31) -+#define FBC_STAT_COMPRESSED (1<<30) -+#define FBC_STAT_MODIFIED (1<<29) -+#define FBC_STAT_CURRENT_LINE (1<<0) -+#define FBC_CONTROL2 0x03214 -+#define FBC_CTL_FENCE_DBL (0<<4) -+#define FBC_CTL_IDLE_IMM (0<<2) -+#define FBC_CTL_IDLE_FULL (1<<2) -+#define FBC_CTL_IDLE_LINE (2<<2) -+#define FBC_CTL_IDLE_DEBUG (3<<2) -+#define FBC_CTL_CPU_FENCE (1<<1) -+#define FBC_CTL_PLANEA (0<<0) -+#define FBC_CTL_PLANEB (1<<0) -+#define FBC_FENCE_OFF 0x0321b -+ -+#define FBC_LL_SIZE (1536) -+ -+/* -+ * GPIO regs -+ */ -+#define GPIOA 0x5010 -+#define GPIOB 0x5014 -+#define GPIOC 0x5018 -+#define GPIOD 0x501c -+#define GPIOE 0x5020 -+#define GPIOF 0x5024 -+#define GPIOG 0x5028 -+#define GPIOH 0x502c -+# define GPIO_CLOCK_DIR_MASK (1 << 0) -+# define GPIO_CLOCK_DIR_IN (0 << 1) -+# define GPIO_CLOCK_DIR_OUT (1 << 1) -+# define GPIO_CLOCK_VAL_MASK (1 << 2) -+# define GPIO_CLOCK_VAL_OUT (1 << 3) -+# define GPIO_CLOCK_VAL_IN (1 << 4) -+# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) -+# define GPIO_DATA_DIR_MASK (1 << 8) -+# define GPIO_DATA_DIR_IN (0 << 9) -+# define GPIO_DATA_DIR_OUT (1 << 9) -+# define GPIO_DATA_VAL_MASK (1 << 10) -+# define GPIO_DATA_VAL_OUT (1 << 11) -+# define GPIO_DATA_VAL_IN (1 << 12) -+# define GPIO_DATA_PULLUP_DISABLE (1 << 13) -+ -+/* -+ * Clock control & power management -+ */ -+ -+#define VGA0 0x6000 -+#define VGA1 0x6004 -+#define VGA_PD 0x6010 -+#define VGA0_PD_P2_DIV_4 (1 << 7) -+#define VGA0_PD_P1_DIV_2 (1 << 5) -+#define VGA0_PD_P1_SHIFT 0 -+#define VGA0_PD_P1_MASK (0x1f << 0) -+#define VGA1_PD_P2_DIV_4 (1 << 15) -+#define VGA1_PD_P1_DIV_2 (1 << 13) -+#define VGA1_PD_P1_SHIFT 8 -+#define VGA1_PD_P1_MASK (0x1f << 8) -+#define DPLL_A 0x06014 -+#define DPLL_B 0x06018 -+#define DPLL_VCO_ENABLE (1 << 31) -+#define DPLL_DVO_HIGH_SPEED (1 << 30) -+#define DPLL_SYNCLOCK_ENABLE (1 << 29) -+#define DPLL_VGA_MODE_DIS (1 << 28) -+#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -+#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -+#define DPLL_MODE_MASK (3 << 26) -+#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -+#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -+#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -+#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -+#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -+#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -+ -+#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) -+#define I915_CRC_ERROR_ENABLE (1UL<<29) -+#define I915_CRC_DONE_ENABLE (1UL<<28) -+#define I915_GMBUS_EVENT_ENABLE (1UL<<27) -+#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) -+#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -+#define I915_DPST_EVENT_ENABLE (1UL<<23) -+#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -+#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -+#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -+#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -+#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) -+#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) -+#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -+#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -+#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) -+#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) -+#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -+#define I915_DPST_EVENT_STATUS (1UL<<7) -+#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) -+#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -+#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -+#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -+#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) -+#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) -+ -+#define SRX_INDEX 0x3c4 -+#define SRX_DATA 0x3c5 -+#define SR01 1 -+#define SR01_SCREEN_OFF (1<<5) -+ -+#define PPCR 0x61204 -+#define PPCR_ON (1<<0) -+ -+#define DVOB 0x61140 -+#define DVOB_ON (1<<31) -+#define DVOC 0x61160 -+#define DVOC_ON (1<<31) -+#define LVDS 0x61180 -+#define LVDS_ON (1<<31) -+ -+#define ADPA 0x61100 -+#define ADPA_DPMS_MASK (~(3<<10)) -+#define ADPA_DPMS_ON (0<<10) -+#define ADPA_DPMS_SUSPEND (1<<10) -+#define ADPA_DPMS_STANDBY (2<<10) -+#define ADPA_DPMS_OFF (3<<10) -+ -+#define RING_TAIL 0x00 -+#define TAIL_ADDR 0x001FFFF8 -+#define RING_HEAD 0x04 -+#define HEAD_WRAP_COUNT 0xFFE00000 -+#define HEAD_WRAP_ONE 0x00200000 -+#define HEAD_ADDR 0x001FFFFC -+#define RING_START 0x08 -+#define START_ADDR 0xFFFFF000 -+#define RING_LEN 0x0C -+#define RING_NR_PAGES 0x001FF000 -+#define RING_REPORT_MASK 0x00000006 -+#define RING_REPORT_64K 0x00000002 -+#define RING_REPORT_128K 0x00000004 -+#define RING_NO_REPORT 0x00000000 -+#define RING_VALID_MASK 0x00000001 -+#define RING_VALID 0x00000001 -+#define RING_INVALID 0x00000000 -+ -+/* Scratch pad debug 0 reg: -+ */ -+#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 -+/* -+ * The i830 generation, in LVDS mode, defines P1 as the bit number set within -+ * this field (only one bit may be set). -+ */ -+#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -+#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -+/* i830, required in DVO non-gang */ -+#define PLL_P2_DIVIDE_BY_4 (1 << 23) -+#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -+#define PLL_REF_INPUT_DREFCLK (0 << 13) -+#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -+#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -+#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -+#define PLL_REF_INPUT_MASK (3 << 13) -+#define PLL_LOAD_PULSE_PHASE_SHIFT 9 -+/* -+ * Parallel to Serial Load Pulse phase selection. -+ * Selects the phase for the 10X DPLL clock for the PCIe -+ * digital display port. The range is 4 to 13; 10 or more -+ * is just a flip delay. The default is 6 -+ */ -+#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -+#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) -+/* -+ * SDVO multiplier for 945G/GM. Not used on 965. -+ */ -+#define SDVO_MULTIPLIER_MASK 0x000000ff -+#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -+#define SDVO_MULTIPLIER_SHIFT_VGA 0 -+#define DPLL_A_MD 0x0601c /* 965+ only */ -+/* -+ * UDI pixel divider, controlling how many pixels are stuffed into a packet. -+ * -+ * Value is pixels minus 1. Must be set to 1 pixel for SDVO. -+ */ -+#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -+#define DPLL_MD_UDI_DIVIDER_SHIFT 24 -+/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -+#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -+#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 -+/* -+ * SDVO/UDI pixel multiplier. -+ * -+ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus -+ * clock rate is 10 times the DPLL clock. At low resolution/refresh rate -+ * modes, the bus rate would be below the limits, so SDVO allows for stuffing -+ * dummy bytes in the datastream at an increased clock rate, with both sides of -+ * the link knowing how many bytes are fill. -+ * -+ * So, for a mode with a dotclock of 65Mhz, we would want to double the clock -+ * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be -+ * set to 130Mhz, and the SDVO multiplier set to 2x in this register and -+ * through an SDVO command. -+ * -+ * This register field has values of multiplication factor minus 1, with -+ * a maximum multiplier of 5 for SDVO. -+ */ -+#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -+#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 -+/* -+ * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. -+ * This best be set to the default value (3) or the CRT won't work. No, -+ * I don't entirely understand what this does... -+ */ -+#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -+#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 -+#define DPLL_B_MD 0x06020 /* 965+ only */ -+#define FPA0 0x06040 -+#define FPA1 0x06044 -+#define FPB0 0x06048 -+#define FPB1 0x0604c -+#define FP_N_DIV_MASK 0x003f0000 -+#define FP_N_DIV_SHIFT 16 -+#define FP_M1_DIV_MASK 0x00003f00 -+#define FP_M1_DIV_SHIFT 8 -+#define FP_M2_DIV_MASK 0x0000003f -+#define FP_M2_DIV_SHIFT 0 -+#define DPLL_TEST 0x606c -+#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -+#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -+#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -+#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -+#define DPLLB_TEST_N_BYPASS (1 << 19) -+#define DPLLB_TEST_M_BYPASS (1 << 18) -+#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -+#define DPLLA_TEST_N_BYPASS (1 << 3) -+#define DPLLA_TEST_M_BYPASS (1 << 2) -+#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) -+#define D_STATE 0x6104 -+#define CG_2D_DIS 0x6200 -+#define CG_3D_DIS 0x6204 -+ -+/* -+ * Palette regs -+ */ -+ -+#define PALETTE_A 0x0a000 -+#define PALETTE_B 0x0a800 -+ -+/* -+ * Overlay regs -+ */ -+ -+#define OVADD 0x30000 -+#define DOVSTA 0x30008 -+#define OC_BUF (0x3<<20) -+#define OGAMC5 0x30010 -+#define OGAMC4 0x30014 -+#define OGAMC3 0x30018 -+#define OGAMC2 0x3001c -+#define OGAMC1 0x30020 -+#define OGAMC0 0x30024 -+ -+/* -+ * Display engine regs -+ */ -+ -+/* Pipe A timing regs */ -+#define HTOTAL_A 0x60000 -+#define HBLANK_A 0x60004 -+#define HSYNC_A 0x60008 -+#define VTOTAL_A 0x6000c -+#define VBLANK_A 0x60010 -+#define VSYNC_A 0x60014 -+#define PIPEASRC 0x6001c -+#define BCLRPAT_A 0x60020 -+ -+/* Pipe B timing regs */ -+#define HTOTAL_B 0x61000 -+#define HBLANK_B 0x61004 -+#define HSYNC_B 0x61008 -+#define VTOTAL_B 0x6100c -+#define VBLANK_B 0x61010 -+#define VSYNC_B 0x61014 -+#define PIPEBSRC 0x6101c -+#define BCLRPAT_B 0x61020 -+ -+/* VGA port control */ -+#define ADPA 0x61100 -+#define ADPA_DAC_ENABLE (1<<31) -+#define ADPA_DAC_DISABLE 0 -+#define ADPA_PIPE_SELECT_MASK (1<<30) -+#define ADPA_PIPE_A_SELECT 0 -+#define ADPA_PIPE_B_SELECT (1<<30) -+#define ADPA_USE_VGA_HVPOLARITY (1<<15) -+#define ADPA_SETS_HVPOLARITY 0 -+#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -+#define ADPA_VSYNC_CNTL_ENABLE 0 -+#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -+#define ADPA_HSYNC_CNTL_ENABLE 0 -+#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -+#define ADPA_VSYNC_ACTIVE_LOW 0 -+#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -+#define ADPA_HSYNC_ACTIVE_LOW 0 -+#define ADPA_DPMS_MASK (~(3<<10)) -+#define ADPA_DPMS_ON (0<<10) -+#define ADPA_DPMS_SUSPEND (1<<10) -+#define ADPA_DPMS_STANDBY (2<<10) -+#define ADPA_DPMS_OFF (3<<10) -+ -+/* Hotplug control (945+ only) */ -+#define PORT_HOTPLUG_EN 0x61110 -+#define SDVOB_HOTPLUG_INT_EN (1 << 26) -+#define SDVOC_HOTPLUG_INT_EN (1 << 25) -+#define TV_HOTPLUG_INT_EN (1 << 18) -+#define CRT_HOTPLUG_INT_EN (1 << 9) -+#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) -+ -+#define PORT_HOTPLUG_STAT 0x61114 -+#define CRT_HOTPLUG_INT_STATUS (1 << 11) -+#define TV_HOTPLUG_INT_STATUS (1 << 10) -+#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -+#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -+#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -+#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -+#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -+#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) -+ -+/* SDVO port control */ -+#define SDVOB 0x61140 -+#define SDVOC 0x61160 -+#define SDVO_ENABLE (1 << 31) -+#define SDVO_PIPE_B_SELECT (1 << 30) -+#define SDVO_STALL_SELECT (1 << 29) -+#define SDVO_INTERRUPT_ENABLE (1 << 26) -+/** -+ * 915G/GM SDVO pixel multiplier. -+ * -+ * Programmed value is multiplier - 1, up to 5x. -+ * -+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK -+ */ -+#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -+#define SDVO_PORT_MULTIPLY_SHIFT 23 -+#define SDVO_PHASE_SELECT_MASK (15 << 19) -+#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -+#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -+#define SDVOC_GANG_MODE (1 << 16) -+#define SDVO_BORDER_ENABLE (1 << 7) -+#define SDVOB_PCIE_CONCURRENCY (1 << 3) -+#define SDVO_DETECTED (1 << 2) -+/* Bits to be preserved when writing */ -+#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -+#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) -+ -+/* DVO port control */ -+#define DVOA 0x61120 -+#define DVOB 0x61140 -+#define DVOC 0x61160 -+#define DVO_ENABLE (1 << 31) -+#define DVO_PIPE_B_SELECT (1 << 30) -+#define DVO_PIPE_STALL_UNUSED (0 << 28) -+#define DVO_PIPE_STALL (1 << 28) -+#define DVO_PIPE_STALL_TV (2 << 28) -+#define DVO_PIPE_STALL_MASK (3 << 28) -+#define DVO_USE_VGA_SYNC (1 << 15) -+#define DVO_DATA_ORDER_I740 (0 << 14) -+#define DVO_DATA_ORDER_FP (1 << 14) -+#define DVO_VSYNC_DISABLE (1 << 11) -+#define DVO_HSYNC_DISABLE (1 << 10) -+#define DVO_VSYNC_TRISTATE (1 << 9) -+#define DVO_HSYNC_TRISTATE (1 << 8) -+#define DVO_BORDER_ENABLE (1 << 7) -+#define DVO_DATA_ORDER_GBRG (1 << 6) -+#define DVO_DATA_ORDER_RGGB (0 << 6) -+#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -+#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -+#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -+#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -+#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -+#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -+#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -+#define DVO_PRESERVE_MASK (0x7<<24) -+#define DVOA_SRCDIM 0x61124 -+#define DVOB_SRCDIM 0x61144 -+#define DVOC_SRCDIM 0x61164 -+#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -+#define DVO_SRCDIM_VERTICAL_SHIFT 0 -+ -+/* LVDS port control */ -+#define LVDS 0x61180 -+/* -+ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as -+ * the DPLL semantics change when the LVDS is assigned to that pipe. -+ */ -+#define LVDS_PORT_EN (1 << 31) -+/* Selects pipe B for LVDS data. Must be set on pre-965. */ -+#define LVDS_PIPEB_SELECT (1 << 30) -+/* -+ * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per -+ * pixel. -+ */ -+#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -+#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -+#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) -+/* -+ * Controls the A3 data pair, which contains the additional LSBs for 24 bit -+ * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be -+ * on. -+ */ -+#define LVDS_A3_POWER_MASK (3 << 6) -+#define LVDS_A3_POWER_DOWN (0 << 6) -+#define LVDS_A3_POWER_UP (3 << 6) -+/* -+ * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP -+ * is set. -+ */ -+#define LVDS_CLKB_POWER_MASK (3 << 4) -+#define LVDS_CLKB_POWER_DOWN (0 << 4) -+#define LVDS_CLKB_POWER_UP (3 << 4) -+/* -+ * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 -+ * setting for whether we are in dual-channel mode. The B3 pair will -+ * additionally only be powered up when LVDS_A3_POWER_UP is set. -+ */ -+#define LVDS_B0B3_POWER_MASK (3 << 2) -+#define LVDS_B0B3_POWER_DOWN (0 << 2) -+#define LVDS_B0B3_POWER_UP (3 << 2) -+ -+/* Panel power sequencing */ -+#define PP_STATUS 0x61200 -+#define PP_ON (1 << 31) -+/* -+ * Indicates that all dependencies of the panel are on: -+ * -+ * - PLL enabled -+ * - pipe enabled -+ * - LVDS/DVOB/DVOC on -+ */ -+#define PP_READY (1 << 30) -+#define PP_SEQUENCE_NONE (0 << 28) -+#define PP_SEQUENCE_ON (1 << 28) -+#define PP_SEQUENCE_OFF (2 << 28) -+#define PP_SEQUENCE_MASK 0x30000000 -+#define PP_CONTROL 0x61204 -+#define POWER_TARGET_ON (1 << 0) -+#define PP_ON_DELAYS 0x61208 -+#define PP_OFF_DELAYS 0x6120c -+#define PP_DIVISOR 0x61210 -+ -+/* Panel fitting */ -+#define PFIT_CONTROL 0x61230 -+#define PFIT_ENABLE (1 << 31) -+#define PFIT_PIPE_MASK (3 << 29) -+#define PFIT_PIPE_SHIFT 29 -+#define VERT_INTERP_DISABLE (0 << 10) -+#define VERT_INTERP_BILINEAR (1 << 10) -+#define VERT_INTERP_MASK (3 << 10) -+#define VERT_AUTO_SCALE (1 << 9) -+#define HORIZ_INTERP_DISABLE (0 << 6) -+#define HORIZ_INTERP_BILINEAR (1 << 6) -+#define HORIZ_INTERP_MASK (3 << 6) -+#define HORIZ_AUTO_SCALE (1 << 5) -+#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -+#define PFIT_PGM_RATIOS 0x61234 -+#define PFIT_VERT_SCALE_MASK 0xfff00000 -+#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 -+#define PFIT_AUTO_RATIOS 0x61238 -+ -+/* Backlight control */ -+#define BLC_PWM_CTL 0x61254 -+#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) -+#define BLC_PWM_CTL2 0x61250 /* 965+ only */ -+/* -+ * This is the most significant 15 bits of the number of backlight cycles in a -+ * complete cycle of the modulated backlight control. -+ * -+ * The actual value is this field multiplied by two. -+ */ -+#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -+#define BLM_LEGACY_MODE (1 << 16) -+/* -+ * This is the number of cycles out of the backlight modulation cycle for which -+ * the backlight is on. -+ * -+ * This field must be no greater than the number of cycles in the complete -+ * backlight modulation cycle. -+ */ -+#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -+#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) -+ -+/* TV port control */ -+#define TV_CTL 0x68000 -+/** Enables the TV encoder */ -+# define TV_ENC_ENABLE (1 << 31) -+/** Sources the TV encoder input from pipe B instead of A. */ -+# define TV_ENC_PIPEB_SELECT (1 << 30) -+/** Outputs composite video (DAC A only) */ -+# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) -+/** Outputs SVideo video (DAC B/C) */ -+# define TV_ENC_OUTPUT_SVIDEO (1 << 28) -+/** Outputs Component video (DAC A/B/C) */ -+# define TV_ENC_OUTPUT_COMPONENT (2 << 28) -+/** Outputs Composite and SVideo (DAC A/B/C) */ -+# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) -+# define TV_TRILEVEL_SYNC (1 << 21) -+/** Enables slow sync generation (945GM only) */ -+# define TV_SLOW_SYNC (1 << 20) -+/** Selects 4x oversampling for 480i and 576p */ -+# define TV_OVERSAMPLE_4X (0 << 18) -+/** Selects 2x oversampling for 720p and 1080i */ -+# define TV_OVERSAMPLE_2X (1 << 18) -+/** Selects no oversampling for 1080p */ -+# define TV_OVERSAMPLE_NONE (2 << 18) -+/** Selects 8x oversampling */ -+# define TV_OVERSAMPLE_8X (3 << 18) -+/** Selects progressive mode rather than interlaced */ -+# define TV_PROGRESSIVE (1 << 17) -+/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ -+# define TV_PAL_BURST (1 << 16) -+/** Field for setting delay of Y compared to C */ -+# define TV_YC_SKEW_MASK (7 << 12) -+/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ -+# define TV_ENC_SDP_FIX (1 << 11) -+/** -+ * Enables a fix for the 915GM only. -+ * -+ * Not sure what it does. -+ */ -+# define TV_ENC_C0_FIX (1 << 10) -+/** Bits that must be preserved by software */ -+# define TV_CTL_SAVE ((3 << 8) | (3 << 6)) -+# define TV_FUSE_STATE_MASK (3 << 4) -+/** Read-only state that reports all features enabled */ -+# define TV_FUSE_STATE_ENABLED (0 << 4) -+/** Read-only state that reports that Macrovision is disabled in hardware*/ -+# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) -+/** Read-only state that reports that TV-out is disabled in hardware. */ -+# define TV_FUSE_STATE_DISABLED (2 << 4) -+/** Normal operation */ -+# define TV_TEST_MODE_NORMAL (0 << 0) -+/** Encoder test pattern 1 - combo pattern */ -+# define TV_TEST_MODE_PATTERN_1 (1 << 0) -+/** Encoder test pattern 2 - full screen vertical 75% color bars */ -+# define TV_TEST_MODE_PATTERN_2 (2 << 0) -+/** Encoder test pattern 3 - full screen horizontal 75% color bars */ -+# define TV_TEST_MODE_PATTERN_3 (3 << 0) -+/** Encoder test pattern 4 - random noise */ -+# define TV_TEST_MODE_PATTERN_4 (4 << 0) -+/** Encoder test pattern 5 - linear color ramps */ -+# define TV_TEST_MODE_PATTERN_5 (5 << 0) -+/** -+ * This test mode forces the DACs to 50% of full output. -+ * -+ * This is used for load detection in combination with TVDAC_SENSE_MASK -+ */ -+# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) -+# define TV_TEST_MODE_MASK (7 << 0) -+ -+#define TV_DAC 0x68004 -+/** -+ * Reports that DAC state change logic has reported change (RO). -+ * -+ * This gets cleared when TV_DAC_STATE_EN is cleared -+*/ -+# define TVDAC_STATE_CHG (1 << 31) -+# define TVDAC_SENSE_MASK (7 << 28) -+/** Reports that DAC A voltage is above the detect threshold */ -+# define TVDAC_A_SENSE (1 << 30) -+/** Reports that DAC B voltage is above the detect threshold */ -+# define TVDAC_B_SENSE (1 << 29) -+/** Reports that DAC C voltage is above the detect threshold */ -+# define TVDAC_C_SENSE (1 << 28) -+/** -+ * Enables DAC state detection logic, for load-based TV detection. -+ * -+ * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set -+ * to off, for load detection to work. -+ */ -+# define TVDAC_STATE_CHG_EN (1 << 27) -+/** Sets the DAC A sense value to high */ -+# define TVDAC_A_SENSE_CTL (1 << 26) -+/** Sets the DAC B sense value to high */ -+# define TVDAC_B_SENSE_CTL (1 << 25) -+/** Sets the DAC C sense value to high */ -+# define TVDAC_C_SENSE_CTL (1 << 24) -+/** Overrides the ENC_ENABLE and DAC voltage levels */ -+# define DAC_CTL_OVERRIDE (1 << 7) -+/** Sets the slew rate. Must be preserved in software */ -+# define ENC_TVDAC_SLEW_FAST (1 << 6) -+# define DAC_A_1_3_V (0 << 4) -+# define DAC_A_1_1_V (1 << 4) -+# define DAC_A_0_7_V (2 << 4) -+# define DAC_A_OFF (3 << 4) -+# define DAC_B_1_3_V (0 << 2) -+# define DAC_B_1_1_V (1 << 2) -+# define DAC_B_0_7_V (2 << 2) -+# define DAC_B_OFF (3 << 2) -+# define DAC_C_1_3_V (0 << 0) -+# define DAC_C_1_1_V (1 << 0) -+# define DAC_C_0_7_V (2 << 0) -+# define DAC_C_OFF (3 << 0) -+ -+/** -+ * CSC coefficients are stored in a floating point format with 9 bits of -+ * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, -+ * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with -+ * -1 (0x3) being the only legal negative value. -+ */ -+#define TV_CSC_Y 0x68010 -+# define TV_RY_MASK 0x07ff0000 -+# define TV_RY_SHIFT 16 -+# define TV_GY_MASK 0x00000fff -+# define TV_GY_SHIFT 0 -+ -+#define TV_CSC_Y2 0x68014 -+# define TV_BY_MASK 0x07ff0000 -+# define TV_BY_SHIFT 16 -+/** -+ * Y attenuation for component video. -+ * -+ * Stored in 1.9 fixed point. -+ */ -+# define TV_AY_MASK 0x000003ff -+# define TV_AY_SHIFT 0 -+ -+#define TV_CSC_U 0x68018 -+# define TV_RU_MASK 0x07ff0000 -+# define TV_RU_SHIFT 16 -+# define TV_GU_MASK 0x000007ff -+# define TV_GU_SHIFT 0 -+ -+#define TV_CSC_U2 0x6801c -+# define TV_BU_MASK 0x07ff0000 -+# define TV_BU_SHIFT 16 -+/** -+ * U attenuation for component video. -+ * -+ * Stored in 1.9 fixed point. -+ */ -+# define TV_AU_MASK 0x000003ff -+# define TV_AU_SHIFT 0 -+ -+#define TV_CSC_V 0x68020 -+# define TV_RV_MASK 0x0fff0000 -+# define TV_RV_SHIFT 16 -+# define TV_GV_MASK 0x000007ff -+# define TV_GV_SHIFT 0 -+ -+#define TV_CSC_V2 0x68024 -+# define TV_BV_MASK 0x07ff0000 -+# define TV_BV_SHIFT 16 -+/** -+ * V attenuation for component video. -+ * -+ * Stored in 1.9 fixed point. -+ */ -+# define TV_AV_MASK 0x000007ff -+# define TV_AV_SHIFT 0 -+ -+#define TV_CLR_KNOBS 0x68028 -+/** 2s-complement brightness adjustment */ -+# define TV_BRIGHTNESS_MASK 0xff000000 -+# define TV_BRIGHTNESS_SHIFT 24 -+/** Contrast adjustment, as a 2.6 unsigned floating point number */ -+# define TV_CONTRAST_MASK 0x00ff0000 -+# define TV_CONTRAST_SHIFT 16 -+/** Saturation adjustment, as a 2.6 unsigned floating point number */ -+# define TV_SATURATION_MASK 0x0000ff00 -+# define TV_SATURATION_SHIFT 8 -+/** Hue adjustment, as an integer phase angle in degrees */ -+# define TV_HUE_MASK 0x000000ff -+# define TV_HUE_SHIFT 0 -+ -+#define TV_CLR_LEVEL 0x6802c -+/** Controls the DAC level for black */ -+# define TV_BLACK_LEVEL_MASK 0x01ff0000 -+# define TV_BLACK_LEVEL_SHIFT 16 -+/** Controls the DAC level for blanking */ -+# define TV_BLANK_LEVEL_MASK 0x000001ff -+# define TV_BLANK_LEVEL_SHIFT 0 -+ -+#define TV_H_CTL_1 0x68030 -+/** Number of pixels in the hsync. */ -+# define TV_HSYNC_END_MASK 0x1fff0000 -+# define TV_HSYNC_END_SHIFT 16 -+/** Total number of pixels minus one in the line (display and blanking). */ -+# define TV_HTOTAL_MASK 0x00001fff -+# define TV_HTOTAL_SHIFT 0 -+ -+#define TV_H_CTL_2 0x68034 -+/** Enables the colorburst (needed for non-component color) */ -+# define TV_BURST_ENA (1 << 31) -+/** Offset of the colorburst from the start of hsync, in pixels minus one. */ -+# define TV_HBURST_START_SHIFT 16 -+# define TV_HBURST_START_MASK 0x1fff0000 -+/** Length of the colorburst */ -+# define TV_HBURST_LEN_SHIFT 0 -+# define TV_HBURST_LEN_MASK 0x0001fff -+ -+#define TV_H_CTL_3 0x68038 -+/** End of hblank, measured in pixels minus one from start of hsync */ -+# define TV_HBLANK_END_SHIFT 16 -+# define TV_HBLANK_END_MASK 0x1fff0000 -+/** Start of hblank, measured in pixels minus one from start of hsync */ -+# define TV_HBLANK_START_SHIFT 0 -+# define TV_HBLANK_START_MASK 0x0001fff -+ -+#define TV_V_CTL_1 0x6803c -+/** XXX */ -+# define TV_NBR_END_SHIFT 16 -+# define TV_NBR_END_MASK 0x07ff0000 -+/** XXX */ -+# define TV_VI_END_F1_SHIFT 8 -+# define TV_VI_END_F1_MASK 0x00003f00 -+/** XXX */ -+# define TV_VI_END_F2_SHIFT 0 -+# define TV_VI_END_F2_MASK 0x0000003f -+ -+#define TV_V_CTL_2 0x68040 -+/** Length of vsync, in half lines */ -+# define TV_VSYNC_LEN_MASK 0x07ff0000 -+# define TV_VSYNC_LEN_SHIFT 16 -+/** Offset of the start of vsync in field 1, measured in one less than the -+ * number of half lines. -+ */ -+# define TV_VSYNC_START_F1_MASK 0x00007f00 -+# define TV_VSYNC_START_F1_SHIFT 8 -+/** -+ * Offset of the start of vsync in field 2, measured in one less than the -+ * number of half lines. -+ */ -+# define TV_VSYNC_START_F2_MASK 0x0000007f -+# define TV_VSYNC_START_F2_SHIFT 0 -+ -+#define TV_V_CTL_3 0x68044 -+/** Enables generation of the equalization signal */ -+# define TV_EQUAL_ENA (1 << 31) -+/** Length of vsync, in half lines */ -+# define TV_VEQ_LEN_MASK 0x007f0000 -+# define TV_VEQ_LEN_SHIFT 16 -+/** Offset of the start of equalization in field 1, measured in one less than -+ * the number of half lines. -+ */ -+# define TV_VEQ_START_F1_MASK 0x0007f00 -+# define TV_VEQ_START_F1_SHIFT 8 -+/** -+ * Offset of the start of equalization in field 2, measured in one less than -+ * the number of half lines. -+ */ -+# define TV_VEQ_START_F2_MASK 0x000007f -+# define TV_VEQ_START_F2_SHIFT 0 -+ -+#define TV_V_CTL_4 0x68048 -+/** -+ * Offset to start of vertical colorburst, measured in one less than the -+ * number of lines from vertical start. -+ */ -+# define TV_VBURST_START_F1_MASK 0x003f0000 -+# define TV_VBURST_START_F1_SHIFT 16 -+/** -+ * Offset to the end of vertical colorburst, measured in one less than the -+ * number of lines from the start of NBR. -+ */ -+# define TV_VBURST_END_F1_MASK 0x000000ff -+# define TV_VBURST_END_F1_SHIFT 0 -+ -+#define TV_V_CTL_5 0x6804c -+/** -+ * Offset to start of vertical colorburst, measured in one less than the -+ * number of lines from vertical start. -+ */ -+# define TV_VBURST_START_F2_MASK 0x003f0000 -+# define TV_VBURST_START_F2_SHIFT 16 -+/** -+ * Offset to the end of vertical colorburst, measured in one less than the -+ * number of lines from the start of NBR. -+ */ -+# define TV_VBURST_END_F2_MASK 0x000000ff -+# define TV_VBURST_END_F2_SHIFT 0 -+ -+#define TV_V_CTL_6 0x68050 -+/** -+ * Offset to start of vertical colorburst, measured in one less than the -+ * number of lines from vertical start. -+ */ -+# define TV_VBURST_START_F3_MASK 0x003f0000 -+# define TV_VBURST_START_F3_SHIFT 16 -+/** -+ * Offset to the end of vertical colorburst, measured in one less than the -+ * number of lines from the start of NBR. -+ */ -+# define TV_VBURST_END_F3_MASK 0x000000ff -+# define TV_VBURST_END_F3_SHIFT 0 -+ -+#define TV_V_CTL_7 0x68054 -+/** -+ * Offset to start of vertical colorburst, measured in one less than the -+ * number of lines from vertical start. -+ */ -+# define TV_VBURST_START_F4_MASK 0x003f0000 -+# define TV_VBURST_START_F4_SHIFT 16 -+/** -+ * Offset to the end of vertical colorburst, measured in one less than the -+ * number of lines from the start of NBR. -+ */ -+# define TV_VBURST_END_F4_MASK 0x000000ff -+# define TV_VBURST_END_F4_SHIFT 0 -+ -+#define TV_SC_CTL_1 0x68060 -+/** Turns on the first subcarrier phase generation DDA */ -+# define TV_SC_DDA1_EN (1 << 31) -+/** Turns on the first subcarrier phase generation DDA */ -+# define TV_SC_DDA2_EN (1 << 30) -+/** Turns on the first subcarrier phase generation DDA */ -+# define TV_SC_DDA3_EN (1 << 29) -+/** Sets the subcarrier DDA to reset frequency every other field */ -+# define TV_SC_RESET_EVERY_2 (0 << 24) -+/** Sets the subcarrier DDA to reset frequency every fourth field */ -+# define TV_SC_RESET_EVERY_4 (1 << 24) -+/** Sets the subcarrier DDA to reset frequency every eighth field */ -+# define TV_SC_RESET_EVERY_8 (2 << 24) -+/** Sets the subcarrier DDA to never reset the frequency */ -+# define TV_SC_RESET_NEVER (3 << 24) -+/** Sets the peak amplitude of the colorburst.*/ -+# define TV_BURST_LEVEL_MASK 0x00ff0000 -+# define TV_BURST_LEVEL_SHIFT 16 -+/** Sets the increment of the first subcarrier phase generation DDA */ -+# define TV_SCDDA1_INC_MASK 0x00000fff -+# define TV_SCDDA1_INC_SHIFT 0 -+ -+#define TV_SC_CTL_2 0x68064 -+/** Sets the rollover for the second subcarrier phase generation DDA */ -+# define TV_SCDDA2_SIZE_MASK 0x7fff0000 -+# define TV_SCDDA2_SIZE_SHIFT 16 -+/** Sets the increent of the second subcarrier phase generation DDA */ -+# define TV_SCDDA2_INC_MASK 0x00007fff -+# define TV_SCDDA2_INC_SHIFT 0 -+ -+#define TV_SC_CTL_3 0x68068 -+/** Sets the rollover for the third subcarrier phase generation DDA */ -+# define TV_SCDDA3_SIZE_MASK 0x7fff0000 -+# define TV_SCDDA3_SIZE_SHIFT 16 -+/** Sets the increent of the third subcarrier phase generation DDA */ -+# define TV_SCDDA3_INC_MASK 0x00007fff -+# define TV_SCDDA3_INC_SHIFT 0 -+ -+#define TV_WIN_POS 0x68070 -+/** X coordinate of the display from the start of horizontal active */ -+# define TV_XPOS_MASK 0x1fff0000 -+# define TV_XPOS_SHIFT 16 -+/** Y coordinate of the display from the start of vertical active (NBR) */ -+# define TV_YPOS_MASK 0x00000fff -+# define TV_YPOS_SHIFT 0 -+ -+#define TV_WIN_SIZE 0x68074 -+/** Horizontal size of the display window, measured in pixels*/ -+# define TV_XSIZE_MASK 0x1fff0000 -+# define TV_XSIZE_SHIFT 16 -+/** -+ * Vertical size of the display window, measured in pixels. -+ * -+ * Must be even for interlaced modes. -+ */ -+# define TV_YSIZE_MASK 0x00000fff -+# define TV_YSIZE_SHIFT 0 -+ -+#define TV_FILTER_CTL_1 0x68080 -+/** -+ * Enables automatic scaling calculation. -+ * -+ * If set, the rest of the registers are ignored, and the calculated values can -+ * be read back from the register. -+ */ -+# define TV_AUTO_SCALE (1 << 31) -+/** -+ * Disables the vertical filter. -+ * -+ * This is required on modes more than 1024 pixels wide */ -+# define TV_V_FILTER_BYPASS (1 << 29) -+/** Enables adaptive vertical filtering */ -+# define TV_VADAPT (1 << 28) -+# define TV_VADAPT_MODE_MASK (3 << 26) -+/** Selects the least adaptive vertical filtering mode */ -+# define TV_VADAPT_MODE_LEAST (0 << 26) -+/** Selects the moderately adaptive vertical filtering mode */ -+# define TV_VADAPT_MODE_MODERATE (1 << 26) -+/** Selects the most adaptive vertical filtering mode */ -+# define TV_VADAPT_MODE_MOST (3 << 26) -+/** -+ * Sets the horizontal scaling factor. -+ * -+ * This should be the fractional part of the horizontal scaling factor divided -+ * by the oversampling rate. TV_HSCALE should be less than 1, and set to: -+ * -+ * (src width - 1) / ((oversample * dest width) - 1) -+ */ -+# define TV_HSCALE_FRAC_MASK 0x00003fff -+# define TV_HSCALE_FRAC_SHIFT 0 -+ -+#define TV_FILTER_CTL_2 0x68084 -+/** -+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor. -+ * -+ * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) -+ */ -+# define TV_VSCALE_INT_MASK 0x00038000 -+# define TV_VSCALE_INT_SHIFT 15 -+/** -+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. -+ * -+ * \sa TV_VSCALE_INT_MASK -+ */ -+# define TV_VSCALE_FRAC_MASK 0x00007fff -+# define TV_VSCALE_FRAC_SHIFT 0 -+ -+#define TV_FILTER_CTL_3 0x68088 -+/** -+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor. -+ * -+ * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) -+ * -+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. -+ */ -+# define TV_VSCALE_IP_INT_MASK 0x00038000 -+# define TV_VSCALE_IP_INT_SHIFT 15 -+/** -+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. -+ * -+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. -+ * -+ * \sa TV_VSCALE_IP_INT_MASK -+ */ -+# define TV_VSCALE_IP_FRAC_MASK 0x00007fff -+# define TV_VSCALE_IP_FRAC_SHIFT 0 -+ -+#define TV_CC_CONTROL 0x68090 -+# define TV_CC_ENABLE (1 << 31) -+/** -+ * Specifies which field to send the CC data in. -+ * -+ * CC data is usually sent in field 0. -+ */ -+# define TV_CC_FID_MASK (1 << 27) -+# define TV_CC_FID_SHIFT 27 -+/** Sets the horizontal position of the CC data. Usually 135. */ -+# define TV_CC_HOFF_MASK 0x03ff0000 -+# define TV_CC_HOFF_SHIFT 16 -+/** Sets the vertical position of the CC data. Usually 21 */ -+# define TV_CC_LINE_MASK 0x0000003f -+# define TV_CC_LINE_SHIFT 0 -+ -+#define TV_CC_DATA 0x68094 -+# define TV_CC_RDY (1 << 31) -+/** Second word of CC data to be transmitted. */ -+# define TV_CC_DATA_2_MASK 0x007f0000 -+# define TV_CC_DATA_2_SHIFT 16 -+/** First word of CC data to be transmitted. */ -+# define TV_CC_DATA_1_MASK 0x0000007f -+# define TV_CC_DATA_1_SHIFT 0 -+ -+#define TV_H_LUMA_0 0x68100 -+#define TV_H_LUMA_59 0x681ec -+#define TV_H_CHROMA_0 0x68200 -+#define TV_H_CHROMA_59 0x682ec -+#define TV_V_LUMA_0 0x68300 -+#define TV_V_LUMA_42 0x683a8 -+#define TV_V_CHROMA_0 0x68400 -+#define TV_V_CHROMA_42 0x684a8 -+ -+/* Display & cursor control */ -+ -+/* Pipe A */ -+#define PIPEADSL 0x70000 -+#define PIPEACONF 0x70008 -+#define PIPEACONF_ENABLE (1<<31) -+#define PIPEACONF_DISABLE 0 -+#define PIPEACONF_DOUBLE_WIDE (1<<30) -+#define I965_PIPECONF_ACTIVE (1<<30) -+#define PIPEACONF_SINGLE_WIDE 0 -+#define PIPEACONF_PIPE_UNLOCKED 0 -+#define PIPEACONF_PIPE_LOCKED (1<<25) -+#define PIPEACONF_PALETTE 0 -+#define PIPEACONF_GAMMA (1<<24) -+#define PIPECONF_FORCE_BORDER (1<<25) -+#define PIPECONF_PROGRESSIVE (0 << 21) -+#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -+#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) -+#define PIPEASTAT 0x70024 -+#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -+#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -+#define PIPE_CRC_DONE_ENABLE (1UL<<28) -+#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -+#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -+#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -+#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -+#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -+#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -+#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -+#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -+#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -+#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -+#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -+#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -+#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -+#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -+#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -+#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -+#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -+#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -+#define PIPE_DPST_EVENT_STATUS (1UL<<7) -+#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -+#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -+#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -+#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -+#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -+#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -+#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -+ -+#define DSPARB 0x70030 -+#define DSPARB_CSTART_MASK (0x7f << 7) -+#define DSPARB_CSTART_SHIFT 7 -+#define DSPARB_BSTART_MASK (0x7f) -+#define DSPARB_BSTART_SHIFT 0 -+/* -+ * The two pipe frame counter registers are not synchronized, so -+ * reading a stable value is somewhat tricky. The following code -+ * should work: -+ * -+ * do { -+ * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> -+ * PIPE_FRAME_HIGH_SHIFT; -+ * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> -+ * PIPE_FRAME_LOW_SHIFT); -+ * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> -+ * PIPE_FRAME_HIGH_SHIFT); -+ * } while (high1 != high2); -+ * frame = (high1 << 8) | low1; -+ */ -+#define PIPEAFRAMEHIGH 0x70040 -+#define PIPE_FRAME_HIGH_MASK 0x0000ffff -+#define PIPE_FRAME_HIGH_SHIFT 0 -+#define PIPEAFRAMEPIXEL 0x70044 -+#define PIPE_FRAME_LOW_MASK 0xff000000 -+#define PIPE_FRAME_LOW_SHIFT 24 -+#define PIPE_PIXEL_MASK 0x00ffffff -+#define PIPE_PIXEL_SHIFT 0 -+ -+/* Cursor A & B regs */ -+#define CURACNTR 0x70080 -+#define CURSOR_MODE_DISABLE 0x00 -+#define CURSOR_MODE_64_32B_AX 0x07 -+#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -+#define MCURSOR_GAMMA_ENABLE (1 << 26) -+#define CURABASE 0x70084 -+#define CURAPOS 0x70088 -+#define CURSOR_POS_MASK 0x007FF -+#define CURSOR_POS_SIGN 0x8000 -+#define CURSOR_X_SHIFT 0 -+#define CURSOR_Y_SHIFT 16 -+#define CURBCNTR 0x700c0 -+#define CURBBASE 0x700c4 -+#define CURBPOS 0x700c8 -+ -+/* Display A control */ -+#define DSPACNTR 0x70180 -+#define DISPLAY_PLANE_ENABLE (1<<31) -+#define DISPLAY_PLANE_DISABLE 0 -+#define DISPPLANE_GAMMA_ENABLE (1<<30) -+#define DISPPLANE_GAMMA_DISABLE 0 -+#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -+#define DISPPLANE_8BPP (0x2<<26) -+#define DISPPLANE_15_16BPP (0x4<<26) -+#define DISPPLANE_16BPP (0x5<<26) -+#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -+#define DISPPLANE_32BPP (0x7<<26) -+#define DISPPLANE_STEREO_ENABLE (1<<25) -+#define DISPPLANE_STEREO_DISABLE 0 -+#define DISPPLANE_SEL_PIPE_MASK (1<<24) -+#define DISPPLANE_SEL_PIPE_A 0 -+#define DISPPLANE_SEL_PIPE_B (1<<24) -+#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -+#define DISPPLANE_SRC_KEY_DISABLE 0 -+#define DISPPLANE_LINE_DOUBLE (1<<20) -+#define DISPPLANE_NO_LINE_DOUBLE 0 -+#define DISPPLANE_STEREO_POLARITY_FIRST 0 -+#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -+#define DSPAADDR 0x70184 -+#define DSPASTRIDE 0x70188 -+#define DSPAPOS 0x7018C /* reserved */ -+#define DSPASIZE 0x70190 -+#define DSPASURF 0x7019C /* 965+ only */ -+#define DSPATILEOFF 0x701A4 /* 965+ only */ -+ -+/* VBIOS flags */ -+#define SWF00 0x71410 -+#define SWF01 0x71414 -+#define SWF02 0x71418 -+#define SWF03 0x7141c -+#define SWF04 0x71420 -+#define SWF05 0x71424 -+#define SWF06 0x71428 -+#define SWF10 0x70410 -+#define SWF11 0x70414 -+#define SWF14 0x71420 -+#define SWF30 0x72414 -+#define SWF31 0x72418 -+#define SWF32 0x7241c -+ -+/* Pipe B */ -+#define PIPEBDSL 0x71000 -+#define PIPEBCONF 0x71008 -+#define PIPEBSTAT 0x71024 -+#define PIPEBFRAMEHIGH 0x71040 -+#define PIPEBFRAMEPIXEL 0x71044 -+ -+/* Display B control */ -+#define DSPBCNTR 0x71180 -+#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -+#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -+#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -+#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -+#define DSPBADDR 0x71184 -+#define DSPBSTRIDE 0x71188 -+#define DSPBPOS 0x7118C -+#define DSPBSIZE 0x71190 -+#define DSPBSURF 0x7119C -+#define DSPBTILEOFF 0x711A4 -+ -+/* VBIOS regs */ -+#define VGACNTRL 0x71400 -+# define VGA_DISP_DISABLE (1 << 31) -+# define VGA_2X_MODE (1 << 30) -+# define VGA_PIPE_B_SELECT (1 << 29) -+ -+#endif /* _I915_REG_H_ */ |