diff options
Diffstat (limited to 'meta/packages')
| -rw-r--r-- | meta/packages/drm/files/poulsbo.patch | 2647 | ||||
| -rw-r--r-- | meta/packages/drm/libdrm_2.4.4.bb | 4 |
2 files changed, 2650 insertions, 1 deletions
diff --git a/meta/packages/drm/files/poulsbo.patch b/meta/packages/drm/files/poulsbo.patch new file mode 100644 index 000000000..7dda90a2f --- /dev/null +++ b/meta/packages/drm/files/poulsbo.patch @@ -0,0 +1,2647 @@ +Index: libdrm-2.4.4/libdrm/xf86drm.c +=================================================================== +--- libdrm-2.4.4.orig/libdrm/xf86drm.c 2009-01-10 01:08:29.000000000 +0000 ++++ libdrm-2.4.4/libdrm/xf86drm.c 2009-02-05 12:23:22.000000000 +0000 +@@ -2402,6 +2402,569 @@ + return 0; + } + ++ ++/* ++ * Valid flags are ++ * DRM_FENCE_FLAG_EMIT ++ * DRM_FENCE_FLAG_SHAREABLE ++ * DRM_FENCE_MASK_DRIVER ++ */ ++ ++int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type, ++ drmFence *fence) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.flags = flags; ++ arg.type = type; ++ arg.fence_class = fence_class; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg)) ++ return -errno; ++ fence->handle = arg.handle; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->flags = arg.flags; ++ fence->signaled = 0; ++ return 0; ++} ++ ++/* ++ * Valid flags are ++ * DRM_FENCE_FLAG_SHAREABLE ++ * DRM_FENCE_MASK_DRIVER ++ */ ++ ++int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.flags = flags; ++ arg.fence_class = fence_class; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg)) ++ return -errno; ++ fence->handle = arg.handle; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->flags = arg.flags; ++ fence->sequence = arg.sequence; ++ fence->signaled = 0; ++ return 0; ++} ++ ++int drmFenceReference(int fd, unsigned handle, drmFence *fence) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = handle; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg)) ++ return -errno; ++ fence->handle = arg.handle; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->flags = arg.flags; ++ fence->signaled = arg.signaled; ++ return 0; ++} ++ ++int drmFenceUnreference(int fd, const drmFence *fence) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = fence->handle; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg)) ++ return -errno; ++ return 0; ++} ++ ++int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = fence->handle; ++ arg.type = flush_type; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg)) ++ return -errno; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->signaled = arg.signaled; ++ return arg.error; ++} ++ ++int drmFenceUpdate(int fd, drmFence *fence) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = fence->handle; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg)) ++ return -errno; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->signaled = arg.signaled; ++ return 0; ++} ++ ++int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType, ++ int *signaled) ++{ ++ if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) || ++ ((fenceType & fence->signaled) != fenceType)) { ++ int ret = drmFenceFlush(fd, fence, fenceType); ++ if (ret) ++ return ret; ++ } ++ ++ *signaled = ((fenceType & fence->signaled) == fenceType); ++ ++ return 0; ++} ++ ++/* ++ * Valid flags are ++ * DRM_FENCE_FLAG_SHAREABLE ++ * DRM_FENCE_MASK_DRIVER ++ */ ++ ++ ++int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type) ++{ ++ drm_fence_arg_t arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.fence_class = fence->fence_class; ++ arg.flags = flags; ++ arg.handle = fence->handle; ++ arg.type = emit_type; ++ ++ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg)) ++ return -errno; ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->signaled = arg.signaled; ++ fence->sequence = arg.sequence; ++ return 0; ++} ++ ++/* ++ * Valid flags are ++ * DRM_FENCE_FLAG_WAIT_LAZY ++ * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS ++ */ ++ ++#define DRM_IOCTL_TIMEOUT_USEC 3000000UL ++ ++static unsigned long ++drmTimeDiff(struct timeval *now, struct timeval *then) ++{ ++ uint64_t val; ++ ++ val = now->tv_sec - then->tv_sec; ++ val *= 1000000LL; ++ val += now->tv_usec; ++ val -= then->tv_usec; ++ ++ return (unsigned long) val; ++} ++ ++static int ++drmIoctlTimeout(int fd, unsigned long request, void *argp) ++{ ++ int haveThen = 0; ++ struct timeval then, now; ++ int ret; ++ ++ do { ++ ret = ioctl(fd, request, argp); ++ if (ret != 0 && errno == EAGAIN) { ++ if (!haveThen) { ++ gettimeofday(&then, NULL); ++ haveThen = 1; ++ } ++ gettimeofday(&now, NULL); ++ } ++ } while (ret != 0 && errno == EAGAIN && ++ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC); ++ ++ if (ret != 0) ++ return ((errno == EAGAIN) ? -EBUSY : -errno); ++ ++ return 0; ++} ++ ++ ++ ++ ++int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type) ++{ ++ drm_fence_arg_t arg; ++ int ret; ++ ++ if (flush_type == 0) { ++ flush_type = fence->type; ++ } ++ ++ if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) { ++ if ((flush_type & fence->signaled) == flush_type) { ++ return 0; ++ } ++ } ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = fence->handle; ++ arg.type = flush_type; ++ arg.flags = flags; ++ ++ ++ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg); ++ if (ret) ++ return ret; ++ ++ fence->fence_class = arg.fence_class; ++ fence->type = arg.type; ++ fence->signaled = arg.signaled; ++ return arg.error; ++} ++ ++static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf) ++{ ++ buf->handle = rep->handle; ++ buf->flags = rep->flags; ++ buf->size = rep->size; ++ buf->offset = rep->offset; ++ buf->mapHandle = rep->arg_handle; ++ buf->mask = rep->proposed_flags; ++ buf->start = rep->buffer_start; ++ buf->fenceFlags = rep->fence_flags; ++ buf->replyFlags = rep->rep_flags; ++ buf->pageAlignment = rep->page_alignment; ++ buf->tileInfo = rep->tile_info; ++ buf->hwTileStride = rep->hw_tile_stride; ++ buf->desiredTileStride = rep->desired_tile_stride; ++} ++ ++ ++ ++int drmBOCreate(int fd, unsigned long size, ++ unsigned pageAlignment, void *user_buffer, ++ uint64_t mask, ++ unsigned hint, drmBO *buf) ++{ ++ struct drm_bo_create_arg arg; ++ struct drm_bo_create_req *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ int ret; ++ ++ memset(buf, 0, sizeof(*buf)); ++ memset(&arg, 0, sizeof(arg)); ++ req->flags = mask; ++ req->hint = hint; ++ req->size = size; ++ req->page_alignment = pageAlignment; ++ req->buffer_start = (unsigned long) user_buffer; ++ ++ buf->virtual = NULL; ++ ++ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg); ++ if (ret) ++ return ret; ++ ++ drmBOCopyReply(rep, buf); ++ buf->virtual = user_buffer; ++ buf->mapCount = 0; ++ ++ return 0; ++} ++ ++int drmBOReference(int fd, unsigned handle, drmBO *buf) ++{ ++ struct drm_bo_reference_info_arg arg; ++ struct drm_bo_handle_arg *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ ++ memset(&arg, 0, sizeof(arg)); ++ req->handle = handle; ++ ++ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg)) ++ return -errno; ++ ++ drmBOCopyReply(rep, buf); ++ buf->mapVirtual = NULL; ++ buf->mapCount = 0; ++ buf->virtual = NULL; ++ ++ return 0; ++} ++ ++int drmBOUnreference(int fd, drmBO *buf) ++{ ++ struct drm_bo_handle_arg arg; ++ ++ if (buf->mapVirtual && buf->mapHandle) { ++ (void) munmap(buf->mapVirtual, buf->start + buf->size); ++ buf->mapVirtual = NULL; ++ buf->virtual = NULL; ++ } ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = buf->handle; ++ ++ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg)) ++ return -errno; ++ ++ buf->handle = 0; ++ return 0; ++} ++ ++ ++/* ++ * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together ++ * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the ++ * call return an -EBUSY if it can' immediately honor the mapping request. ++ */ ++ ++int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint, ++ void **address) ++{ ++ struct drm_bo_map_wait_idle_arg arg; ++ struct drm_bo_info_req *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ int ret = 0; ++ ++ /* ++ * Make sure we have a virtual address of the buffer. ++ */ ++ ++ if (!buf->virtual) { ++ drmAddress virtual; ++ virtual = mmap(0, buf->size + buf->start, ++ PROT_READ | PROT_WRITE, MAP_SHARED, ++ fd, buf->mapHandle); ++ if (virtual == MAP_FAILED) { ++ ret = -errno; ++ } ++ if (ret) ++ return ret; ++ buf->mapVirtual = virtual; ++ buf->virtual = ((char *) virtual) + buf->start; ++ } ++ ++ memset(&arg, 0, sizeof(arg)); ++ req->handle = buf->handle; ++ req->mask = mapFlags; ++ req->hint = mapHint; ++ ++ /* ++ * May hang if the buffer object is busy. ++ * This IOCTL synchronizes the buffer. ++ */ ++ ++ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg); ++ if (ret) ++ return ret; ++ ++ drmBOCopyReply(rep, buf); ++ buf->mapFlags = mapFlags; ++ ++buf->mapCount; ++ *address = buf->virtual; ++ ++ return 0; ++} ++ ++ ++int drmBOUnmap(int fd, drmBO *buf) ++{ ++ struct drm_bo_handle_arg arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.handle = buf->handle; ++ ++ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) { ++ return -errno; ++ } ++ buf->mapCount--; ++ return 0; ++} ++ ++int drmBOSetStatus(int fd, drmBO *buf, ++ uint64_t flags, uint64_t mask, ++ unsigned int hint, ++ unsigned int desired_tile_stride, ++ unsigned int tile_info) ++{ ++ ++ struct drm_bo_map_wait_idle_arg arg; ++ struct drm_bo_info_req *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ int ret = 0; ++ ++ memset(&arg, 0, sizeof(arg)); ++ req->mask = mask; ++ req->flags = flags; ++ req->handle = buf->handle; ++ req->hint = hint; ++ req->desired_tile_stride = desired_tile_stride; ++ req->tile_info = tile_info; ++ ++ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg); ++ if (ret) ++ return ret; ++ ++ drmBOCopyReply(rep, buf); ++ return 0; ++} ++ ++ ++int drmBOInfo(int fd, drmBO *buf) ++{ ++ struct drm_bo_reference_info_arg arg; ++ struct drm_bo_handle_arg *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ int ret = 0; ++ ++ memset(&arg, 0, sizeof(arg)); ++ req->handle = buf->handle; ++ ++ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg); ++ if (ret) ++ return -errno; ++ ++ drmBOCopyReply(rep, buf); ++ return 0; ++} ++ ++int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint) ++{ ++ struct drm_bo_map_wait_idle_arg arg; ++ struct drm_bo_info_req *req = &arg.d.req; ++ struct drm_bo_info_rep *rep = &arg.d.rep; ++ int ret = 0; ++ ++ if ((buf->flags & DRM_BO_FLAG_SHAREABLE) || ++ (buf->replyFlags & DRM_BO_REP_BUSY)) { ++ memset(&arg, 0, sizeof(arg)); ++ req->handle = buf->handle; ++ req->hint = hint; ++ ++ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg); ++ if (ret) ++ return ret; ++ ++ drmBOCopyReply(rep, buf); ++ } ++ return 0; ++} ++ ++int drmBOBusy(int fd, drmBO *buf, int *busy) ++{ ++ if (!(buf->flags & DRM_BO_FLAG_SHAREABLE) && ++ !(buf->replyFlags & DRM_BO_REP_BUSY)) { ++ *busy = 0; ++ return 0; ++ } ++ else { ++ int ret = drmBOInfo(fd, buf); ++ if (ret) ++ return ret; ++ *busy = (buf->replyFlags & DRM_BO_REP_BUSY); ++ return 0; ++ } ++} ++ ++int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize, ++ unsigned memType) ++{ ++ struct drm_mm_init_arg arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ ++ arg.magic = DRM_BO_INIT_MAGIC; ++ arg.major = DRM_BO_INIT_MAJOR; ++ arg.minor = DRM_BO_INIT_MINOR; ++ arg.p_offset = pOffset; ++ arg.p_size = pSize; ++ arg.mem_type = memType; ++ ++ if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg)) ++ return -errno; ++ return 0; ++} ++ ++int drmMMTakedown(int fd, unsigned memType) ++{ ++ struct drm_mm_type_arg arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.mem_type = memType; ++ ++ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg)) ++ return -errno; ++ return 0; ++} ++ ++/* ++ * If this function returns an error, and lockBM was set to 1, ++ * the buffer manager is NOT locked. ++ */ ++ ++int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict) ++{ ++ struct drm_mm_type_arg arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ arg.mem_type = memType; ++ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0; ++ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0; ++ ++ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg); ++} ++ ++int drmMMUnlock(int fd, unsigned memType, int unlockBM) ++{ ++ struct drm_mm_type_arg arg; ++ ++ memset(&arg, 0, sizeof(arg)); ++ ++ arg.mem_type = memType; ++ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0; ++ ++ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg); ++} ++ ++int drmBOVersion(int fd, unsigned int *major, ++ unsigned int *minor, ++ unsigned int *patchlevel) ++{ ++ struct drm_bo_version_arg arg; ++ int ret; ++ ++ memset(&arg, 0, sizeof(arg)); ++ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg); ++ if (ret) ++ return -errno; ++ ++ if (major) ++ *major = arg.major; ++ if (minor) ++ *minor = arg.minor; ++ if (patchlevel) ++ *patchlevel = arg.patchlevel; ++ ++ return 0; ++} ++ ++ ++ + #define DRM_MAX_FDS 16 + static struct { + char *BusID; +Index: libdrm-2.4.4/libdrm/xf86drm.h +=================================================================== +--- libdrm-2.4.4.orig/libdrm/xf86drm.h 2008-12-17 18:28:24.000000000 +0000 ++++ libdrm-2.4.4/libdrm/xf86drm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -665,4 +665,6 @@ + extern int drmSetMaster(int fd); + extern int drmDropMaster(int fd); + ++#include "xf86mm.h" ++ + #endif +Index: libdrm-2.4.4/libdrm/xf86mm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ libdrm-2.4.4/libdrm/xf86mm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -0,0 +1,140 @@ ++/************************************************************************** ++ * ++ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * ++ **************************************************************************/ ++ ++#ifndef _XF86MM_H_ ++#define _XF86MM_H_ ++#include <stddef.h> ++#include <stdint.h> ++#include "drm.h" ++ ++/* ++ * Note on multithreaded applications using this interface. ++ * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to ++ * be protected using an external mutex. ++ * ++ * Note: Don't protect the following functions, as it may lead to deadlocks: ++ * drmBOUnmap(). ++ * The kernel is synchronizing and refcounting buffer maps. ++ * User space only needs to refcount object usage within the same application. ++ */ ++ ++ ++/* ++ * List macros heavily inspired by the Linux kernel ++ * list handling. No list looping yet. ++ */ ++ ++typedef struct _drmFence ++{ ++ unsigned handle; ++ int fence_class; ++ unsigned type; ++ unsigned flags; ++ unsigned signaled; ++ uint32_t sequence; ++ unsigned pad[4]; /* for future expansion */ ++} drmFence; ++ ++typedef struct _drmBO ++{ ++ unsigned handle; ++ uint64_t mapHandle; ++ uint64_t flags; ++ uint64_t mask; ++ unsigned mapFlags; ++ unsigned long size; ++ unsigned long offset; ++ unsigned long start; ++ unsigned replyFlags; ++ unsigned fenceFlags; ++ unsigned pageAlignment; ++ unsigned tileInfo; ++ unsigned hwTileStride; ++ unsigned desiredTileStride; ++ void *virtual; ++ void *mapVirtual; ++ int mapCount; ++ unsigned pad[8]; /* for future expansion */ ++} drmBO; ++ ++/* ++ * Fence functions. ++ */ ++ ++extern int drmFenceCreate(int fd, unsigned flags, int fence_class, ++ unsigned type, drmFence *fence); ++extern int drmFenceReference(int fd, unsigned handle, drmFence *fence); ++extern int drmFenceUnreference(int fd, const drmFence *fence); ++extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type); ++extern int drmFenceSignaled(int fd, drmFence *fence, ++ unsigned fenceType, int *signaled); ++extern int drmFenceWait(int fd, unsigned flags, drmFence *fence, ++ unsigned flush_type); ++extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence, ++ unsigned emit_type); ++extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence); ++ ++ ++/* ++ * Buffer object functions. ++ */ ++ ++extern int drmBOCreate(int fd, unsigned long size, ++ unsigned pageAlignment, void *user_buffer, ++ uint64_t mask, unsigned hint, drmBO *buf); ++extern int drmBOReference(int fd, unsigned handle, drmBO *buf); ++extern int drmBOUnreference(int fd, drmBO *buf); ++extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint, ++ void **address); ++extern int drmBOUnmap(int fd, drmBO *buf); ++extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle); ++extern int drmBOInfo(int fd, drmBO *buf); ++extern int drmBOBusy(int fd, drmBO *buf, int *busy); ++ ++extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint); ++ ++/* ++ * Initialization functions. ++ */ ++ ++extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize, ++ unsigned memType); ++extern int drmMMTakedown(int fd, unsigned memType); ++extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict); ++extern int drmMMUnlock(int fd, unsigned memType, int unlockBM); ++extern int drmBOSetStatus(int fd, drmBO *buf, ++ uint64_t flags, uint64_t mask, ++ unsigned int hint, ++ unsigned int desired_tile_stride, ++ unsigned int tile_info); ++extern int drmBOVersion(int fd, unsigned int *major, ++ unsigned int *minor, ++ unsigned int *patchlevel); ++ ++ ++#endif +Index: libdrm-2.4.4/Makefile.am +=================================================================== +--- libdrm-2.4.4.orig/Makefile.am 2008-10-09 20:02:10.000000000 +0100 ++++ libdrm-2.4.4/Makefile.am 2009-02-04 16:39:55.000000000 +0000 +@@ -22,7 +22,7 @@ + # here too, but let's just do libdrm for now + + AUTOMAKE_OPTIONS = foreign +-SUBDIRS = libdrm shared-core tests ++SUBDIRS = libdrm shared-core + + pkgconfigdir = @pkgconfigdir@ + pkgconfig_DATA = libdrm.pc +Index: libdrm-2.4.4/shared-core/drm.h +=================================================================== +--- libdrm-2.4.4.orig/shared-core/drm.h 2008-12-17 18:28:24.000000000 +0000 ++++ libdrm-2.4.4/shared-core/drm.h 2009-02-05 12:20:53.000000000 +0000 +@@ -632,6 +632,8 @@ + unsigned long handle; /**< Used for mapping / unmapping */ + }; + ++ ++ + /** + * DRM_IOCTL_SET_VERSION ioctl argument type. + */ +@@ -1109,6 +1111,32 @@ + #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t) + #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xB0, struct drm_mode_fb_cmd) + ++#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg) ++#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg) ++#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg) ++#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) ++ ++#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg) ++#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) ++ ++#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) ++#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) ++#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) ++#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) ++#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) ++#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) ++#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) ++#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) ++#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg) ++ ++#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo) ++#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int) + /*@}*/ + + /** +Index: libdrm-2.4.4/shared-core/i915_drm.h +=================================================================== +--- libdrm-2.4.4.orig/shared-core/i915_drm.h 2008-12-23 00:03:35.000000000 +0000 ++++ libdrm-2.4.4/shared-core/i915_drm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -767,4 +767,22 @@ + uint64_t aper_available_size; + }; + ++/* ++ * Relocation header is 4 uint32_ts ++ * 0 - (16-bit relocation type << 16)| 16 bit reloc count ++ * 1 - buffer handle for another list of relocs ++ * 2-3 - spare. ++ */ ++#define I915_RELOC_HEADER 4 ++ ++/* ++ * type 0 relocation has 4-uint32_t stride ++ * 0 - offset into buffer ++ * 1 - delta to add in ++ * 2 - index into buffer list ++ * 3 - reserved (for optimisations later). ++ */ ++#define I915_RELOC_TYPE_0 0 ++#define I915_RELOC0_STRIDE 4 ++ + #endif /* _I915_DRM_H_ */ +Index: libdrm-2.4.4/shared-core/Makefile.am +=================================================================== +--- libdrm-2.4.4.orig/shared-core/Makefile.am 2008-12-17 18:28:24.000000000 +0000 ++++ libdrm-2.4.4/shared-core/Makefile.am 2009-02-04 16:39:55.000000000 +0000 +@@ -31,6 +31,8 @@ + mach64_drm.h \ + mga_drm.h \ + nouveau_drm.h \ ++ psb_drm.h \ ++ psb_reg.h \ + r128_drm.h \ + radeon_drm.h \ + savage_drm.h \ +Index: libdrm-2.4.4/shared-core/nouveau_drm.h +=================================================================== +--- libdrm-2.4.4.orig/shared-core/nouveau_drm.h 2008-10-09 20:02:11.000000000 +0100 ++++ libdrm-2.4.4/shared-core/nouveau_drm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -144,9 +144,12 @@ + NV_05 =5, + NV_10 =10, + NV_11 =11, ++ NV_15 =11, + NV_17 =17, + NV_20 =20, ++ NV_25 =20, + NV_30 =30, ++ NV_34 =30, + NV_40 =40, + NV_44 =44, + NV_50 =50, +Index: libdrm-2.4.4/shared-core/psb_drm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ libdrm-2.4.4/shared-core/psb_drm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -0,0 +1,359 @@ ++/************************************************************************** ++ * Copyright (c) 2007, Intel Corporation. ++ * All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to ++ * develop this driver. ++ * ++ **************************************************************************/ ++/* ++ */ ++ ++#ifndef _PSB_DRM_H_ ++#define _PSB_DRM_H_ ++ ++#if defined(__linux__) && !defined(__KERNEL__) ++#include<stdint.h> ++#endif ++ ++/* ++ * Intel Poulsbo driver package version. ++ * ++ */ ++/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/ ++#define PSB_PACKAGE_VERSION "2.0.0.32L.0007" ++ ++#define DRM_PSB_SAREA_MAJOR 0 ++#define DRM_PSB_SAREA_MINOR 1 ++#define PSB_FIXED_SHIFT 16 ++ ++/* ++ * Public memory types. ++ */ ++ ++#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1 ++#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1 ++#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2 ++#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2 ++#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3 ++#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3 ++#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4 ++#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4 ++#define PSB_MEM_RASTGEOM_START 0x30000000 ++ ++typedef int32_t psb_fixed; ++typedef uint32_t psb_ufixed; ++ ++static inline psb_fixed psb_int_to_fixed(int a) ++{ ++ return a * (1 << PSB_FIXED_SHIFT); ++} ++ ++static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a) ++{ ++ return a << PSB_FIXED_SHIFT; ++} ++ ++/*Status of the command sent to the gfx device.*/ ++typedef enum { ++ DRM_CMD_SUCCESS, ++ DRM_CMD_FAILED, ++ DRM_CMD_HANG ++} drm_cmd_status_t; ++ ++struct drm_psb_scanout { ++ uint32_t buffer_id; /* DRM buffer object ID */ ++ uint32_t rotation; /* Rotation as in RR_rotation definitions */ ++ uint32_t stride; /* Buffer stride in bytes */ ++ uint32_t depth; /* Buffer depth in bits (NOT) bpp */ ++ uint32_t width; /* Buffer width in pixels */ ++ uint32_t height; /* Buffer height in lines */ ++ psb_fixed transform[3][3]; /* Buffer composite transform */ ++ /* (scaling, rot, reflect) */ ++}; ++ ++#define DRM_PSB_SAREA_OWNERS 16 ++#define DRM_PSB_SAREA_OWNER_2D 0 ++#define DRM_PSB_SAREA_OWNER_3D 1 ++ ++#define DRM_PSB_SAREA_SCANOUTS 3 ++ ++struct drm_psb_sarea { ++ /* Track changes of this data structure */ ++ ++ uint32_t major; ++ uint32_t minor; ++ ++ /* Last context to touch part of hw */ ++ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; ++ ++ /* Definition of front- and rotated buffers */ ++ uint32_t num_scanouts; ++ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; ++ ++ int planeA_x; ++ int planeA_y; ++ int planeA_w; ++ int planeA_h; ++ int planeB_x; ++ int planeB_y; ++ int planeB_w; ++ int planeB_h; ++ uint32_t msvdx_state; ++ uint32_t msvdx_context; ++}; ++ ++#define PSB_RELOC_MAGIC 0x67676767 ++#define PSB_RELOC_SHIFT_MASK 0x0000FFFF ++#define PSB_RELOC_SHIFT_SHIFT 0 ++#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 ++#define PSB_RELOC_ALSHIFT_SHIFT 16 ++ ++#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated ++ * buffer ++ */ ++#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated ++ * buffer, relative to 2D ++ * base address ++ */ ++#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer, ++ * relative to PDS base address ++ */ ++#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated ++ * buffer (for tiling) ++ */ ++#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer ++ * relative to base reg ++ */ ++#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */ ++ ++struct drm_psb_reloc { ++ uint32_t reloc_op; ++ uint32_t where; /* offset in destination buffer */ ++ uint32_t buffer; /* Buffer reloc applies to */ ++ uint32_t mask; /* Destination format: */ ++ uint32_t shift; /* Destination format: */ ++ uint32_t pre_add; /* Destination format: */ ++ uint32_t background; /* Destination add */ ++ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */ ++ uint32_t arg0; /* Reloc-op dependant */ ++ uint32_t arg1; ++}; ++ ++#define PSB_BO_FLAG_TA (1ULL << 48) ++#define PSB_BO_FLAG_SCENE (1ULL << 49) ++#define PSB_BO_FLAG_FEEDBACK (1ULL << 50) ++#define PSB_BO_FLAG_USSE (1ULL << 51) ++ ++#define PSB_ENGINE_2D 0 ++#define PSB_ENGINE_VIDEO 1 ++#define PSB_ENGINE_RASTERIZER 2 ++#define PSB_ENGINE_TA 3 ++#define PSB_ENGINE_HPRAST 4 ++ ++/* ++ * For this fence class we have a couple of ++ * fence types. ++ */ ++ ++#define _PSB_FENCE_EXE_SHIFT 0 ++#define _PSB_FENCE_TA_DONE_SHIFT 1 ++#define _PSB_FENCE_RASTER_DONE_SHIFT 2 ++#define _PSB_FENCE_SCENE_DONE_SHIFT 3 ++#define _PSB_FENCE_FEEDBACK_SHIFT 4 ++ ++#define _PSB_ENGINE_TA_FENCE_TYPES 5 ++#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT) ++#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT) ++#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT) ++#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) ++ ++#define PSB_ENGINE_HPRAST 4 ++#define PSB_NUM_ENGINES 5 ++ ++#define PSB_TA_FLAG_FIRSTPASS (1 << 0) ++#define PSB_TA_FLAG_LASTPASS (1 << 1) ++ ++#define PSB_FEEDBACK_OP_VISTEST (1 << 0) ++ ++struct drm_psb_scene { ++ int handle_valid; ++ uint32_t handle; ++ uint32_t w; ++ uint32_t h; ++ uint32_t num_buffers; ++}; ++ ++typedef struct drm_psb_cmdbuf_arg { ++ uint64_t buffer_list; /* List of buffers to validate */ ++ uint64_t clip_rects; /* See i915 counterpart */ ++ uint64_t scene_arg; ++ uint64_t fence_arg; ++ ++ uint32_t ta_flags; ++ ++ uint32_t ta_handle; /* TA reg-value pairs */ ++ uint32_t ta_offset; ++ uint32_t ta_size; ++ ++ uint32_t oom_handle; ++ uint32_t oom_offset; ++ uint32_t oom_size; ++ ++ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */ ++ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */ ++ uint32_t cmdbuf_size; ++ ++ uint32_t reloc_handle; /* Reloc buffer object */ ++ uint32_t reloc_offset; ++ uint32_t num_relocs; ++ ++ int32_t damage; /* Damage front buffer with cliprects */ ++ /* Not implemented yet */ ++ uint32_t fence_flags; ++ uint32_t engine; ++ ++ /* ++ * Feedback; ++ */ ++ ++ uint32_t feedback_ops; ++ uint32_t feedback_handle; ++ uint32_t feedback_offset; ++ uint32_t feedback_breakpoints; ++ uint32_t feedback_size; ++} drm_psb_cmdbuf_arg_t; ++ ++struct drm_psb_xhw_init_arg { ++ uint32_t operation; ++ uint32_t buffer_handle; ++}; ++ ++/* ++ * Feedback components: ++ */ ++ ++/* ++ * Vistest component. The number of these in the feedback buffer ++ * equals the number of vistest breakpoints + 1. ++ * This is currently the only feedback component. ++ */ ++ ++struct drm_psb_vistest { ++ uint32_t vt[8]; ++}; ++ ++#define PSB_HW_COOKIE_SIZE 16 ++#define PSB_HW_FEEDBACK_SIZE 8 ++#define PSB_HW_OOM_CMD_SIZE 6 ++ ++struct drm_psb_xhw_arg { ++ uint32_t op; ++ int ret; ++ uint32_t irq_op; ++ uint32_t issue_irq; ++ uint32_t cookie[PSB_HW_COOKIE_SIZE]; ++ union { ++ struct { ++ uint32_t w; ++ uint32_t h; ++ uint32_t size; ++ uint32_t clear_p_start; ++ uint32_t clear_num_pages; ++ } si; ++ struct { ++ uint32_t fire_flags; ++ uint32_t hw_context; ++ uint32_t offset; ++ uint32_t engine; ++ uint32_t flags; ++ uint32_t rca; ++ uint32_t num_oom_cmds; ++ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE]; ++ } sb; ++ struct { ++ uint32_t pages; ++ uint32_t size; ++ } bi; ++ struct { ++ uint32_t bca; ++ uint32_t rca; ++ uint32_t flags; ++ } oom; ++ struct { ++ uint32_t pt_offset; ++ uint32_t param_offset; ++ uint32_t flags; ++ } bl; ++ uint32_t feedback[PSB_HW_FEEDBACK_SIZE]; ++ } arg; ++}; ++ ++#define DRM_PSB_CMDBUF 0x00 ++#define DRM_PSB_XHW_INIT 0x01 ++#define DRM_PSB_XHW 0x02 ++#define DRM_PSB_SCENE_UNREF 0x03 ++/* Controlling the kernel modesetting buffers */ ++#define DRM_PSB_KMS_OFF 0x04 ++#define DRM_PSB_KMS_ON 0x05 ++ ++#define PSB_XHW_INIT 0x00 ++#define PSB_XHW_TAKEDOWN 0x01 ++ ++#define PSB_XHW_FIRE_RASTER 0x00 ++#define PSB_XHW_SCENE_INFO 0x01 ++#define PSB_XHW_SCENE_BIND_FIRE 0x02 ++#define PSB_XHW_TA_MEM_INFO 0x03 ++#define PSB_XHW_RESET_DPM 0x04 ++#define PSB_XHW_OOM 0x05 ++#define PSB_XHW_TERMINATE 0x06 ++#define PSB_XHW_VISTEST 0x07 ++#define PSB_XHW_RESUME 0x08 ++#define PSB_XHW_TA_MEM_LOAD 0x09 ++ ++#define PSB_SCENE_FLAG_DIRTY (1 << 0) ++#define PSB_SCENE_FLAG_COMPLETE (1 << 1) ++#define PSB_SCENE_FLAG_SETUP (1 << 2) ++#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3) ++#define PSB_SCENE_FLAG_CLEARED (1 << 4) ++ ++#define PSB_TA_MEM_FLAG_TA (1 << 0) ++#define PSB_TA_MEM_FLAG_RASTER (1 << 1) ++#define PSB_TA_MEM_FLAG_HOSTA (1 << 2) ++#define PSB_TA_MEM_FLAG_HOSTD (1 << 3) ++#define PSB_TA_MEM_FLAG_INIT (1 << 4) ++#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5) ++ ++/*Raster fire will deallocate memory */ ++#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0) ++/*Isp reset needed due to change in ZLS format */ ++#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1) ++/*These are set by Xpsb. */ ++#define PSB_FIRE_FLAG_XHW_MASK 0xff000000 ++/*The task has had at least one OOM and Xpsb will ++ send back messages on each fire. */ ++#define PSB_FIRE_FLAG_XHW_OOM (1 << 24) ++ ++#define PSB_SCENE_ENGINE_TA 0 ++#define PSB_SCENE_ENGINE_RASTER 1 ++#define PSB_SCENE_NUM_ENGINES 2 ++ ++struct drm_psb_dev_info_arg { ++ uint32_t num_use_attribute_registers; ++}; ++#define DRM_PSB_DEVINFO 0x01 ++ ++#endif +Index: libdrm-2.4.4/shared-core/psb_drv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ libdrm-2.4.4/shared-core/psb_drv.h 2009-02-04 16:39:55.000000000 +0000 +@@ -0,0 +1,786 @@ ++/************************************************************************** ++ * Copyright (c) 2007, Intel Corporation. ++ * All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to ++ * develop this driver. ++ * ++ **************************************************************************/ ++/* ++ */ ++#ifndef _PSB_DRV_H_ ++#define _PSB_DRV_H_ ++ ++#include "drmP.h" ++#include "psb_drm.h" ++#include "psb_reg.h" ++#include "psb_schedule.h" ++#include "intel_drv.h" ++ ++enum { ++ CHIP_PSB_8108 = 0, ++ CHIP_PSB_8109 = 1 ++}; ++ ++#define DRIVER_NAME "psb" ++#define DRIVER_DESC "drm driver for the Intel GMA500" ++#define DRIVER_AUTHOR "Tungsten Graphics Inc." ++ ++#define PSB_DRM_DRIVER_DATE "20080107" ++#define PSB_DRM_DRIVER_MAJOR 4 ++#define PSB_DRM_DRIVER_MINOR 1 ++#define PSB_DRM_DRIVER_PATCHLEVEL 0 ++ ++#define PSB_VDC_OFFSET 0x00000000 ++#define PSB_VDC_SIZE 0x000080000 ++#define PSB_SGX_SIZE 0x8000 ++#define PSB_SGX_OFFSET 0x00040000 ++#define PSB_MMIO_RESOURCE 0 ++#define PSB_GATT_RESOURCE 2 ++#define PSB_GTT_RESOURCE 3 ++#define PSB_GMCH_CTRL 0x52 ++#define PSB_BSM 0x5C ++#define _PSB_GMCH_ENABLED 0x4 ++#define PSB_PGETBL_CTL 0x2020 ++#define _PSB_PGETBL_ENABLED 0x00000001 ++#define PSB_SGX_2D_SLAVE_PORT 0x4000 ++#define PSB_TT_PRIV0_LIMIT (256*1024*1024) ++#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) ++#define PSB_NUM_VALIDATE_BUFFERS 640 ++#define PSB_MEM_KERNEL_START 0x10000000 ++#define PSB_MEM_PDS_START 0x20000000 ++#define PSB_MEM_MMU_START 0x40000000 ++ ++#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0 ++#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0 ++ ++/* ++ * Flags for external memory type field. ++ */ ++ ++#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */ ++#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */ ++ ++#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ ++#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ ++#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ ++ ++/* ++ * PTE's and PDE's ++ */ ++ ++#define PSB_PDE_MASK 0x003FFFFF ++#define PSB_PDE_SHIFT 22 ++#define PSB_PTE_SHIFT 12 ++ ++#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ ++#define PSB_PTE_WO 0x0002 /* Write only */ ++#define PSB_PTE_RO 0x0004 /* Read only */ ++#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ ++ ++/* ++ * VDC registers and bits ++ */ ++#define PSB_HWSTAM 0x2098 ++#define PSB_INSTPM 0x20C0 ++#define PSB_INT_IDENTITY_R 0x20A4 ++#define _PSB_VSYNC_PIPEB_FLAG (1<<5) ++#define _PSB_VSYNC_PIPEA_FLAG (1<<7) ++#define _PSB_IRQ_SGX_FLAG (1<<18) ++#define _PSB_IRQ_MSVDX_FLAG (1<<19) ++#define PSB_INT_MASK_R 0x20A8 ++#define PSB_INT_ENABLE_R 0x20A0 ++#define PSB_PIPEASTAT 0x70024 ++#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17) ++#define _PSB_VBLANK_CLEAR (1 << 1) ++#define PSB_PIPEBSTAT 0x71024 ++ ++#define _PSB_MMU_ER_MASK 0x0001FF00 ++#define _PSB_MMU_ER_HOST (1 << 16) ++#define GPIOA 0x5010 ++#define GPIOB 0x5014 ++#define GPIOC 0x5018 ++#define GPIOD 0x501c ++#define GPIOE 0x5020 ++#define GPIOF 0x5024 ++#define GPIOG 0x5028 ++#define GPIOH 0x502c ++#define GPIO_CLOCK_DIR_MASK (1 << 0) ++#define GPIO_CLOCK_DIR_IN (0 << 1) ++#define GPIO_CLOCK_DIR_OUT (1 << 1) ++#define GPIO_CLOCK_VAL_MASK (1 << 2) ++#define GPIO_CLOCK_VAL_OUT (1 << 3) ++#define GPIO_CLOCK_VAL_IN (1 << 4) ++#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) ++#define GPIO_DATA_DIR_MASK (1 << 8) ++#define GPIO_DATA_DIR_IN (0 << 9) ++#define GPIO_DATA_DIR_OUT (1 << 9) ++#define GPIO_DATA_VAL_MASK (1 << 10) ++#define GPIO_DATA_VAL_OUT (1 << 11) ++#define GPIO_DATA_VAL_IN (1 << 12) ++#define GPIO_DATA_PULLUP_DISABLE (1 << 13) ++ ++#define VCLK_DIVISOR_VGA0 0x6000 ++#define VCLK_DIVISOR_VGA1 0x6004 ++#define VCLK_POST_DIV 0x6010 ++ ++#define DRM_DRIVER_PRIVATE_T struct drm_psb_private ++#define I915_WRITE(_offs, _val) \ ++ iowrite32(_val, dev_priv->vdc_reg + (_offs)) ++#define I915_READ(_offs) \ ++ ioread32(dev_priv->vdc_reg + (_offs)) ++ ++#define PSB_COMM_2D (PSB_ENGINE_2D << 4) ++#define PSB_COMM_3D (PSB_ENGINE_3D << 4) ++#define PSB_COMM_TA (PSB_ENGINE_TA << 4) ++#define PSB_COMM_HP (PSB_ENGINE_HP << 4) ++#define PSB_COMM_USER_IRQ (1024 >> 2) ++#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) ++#define PSB_COMM_FW (2048 >> 2) ++ ++#define PSB_UIRQ_VISTEST 1 ++#define PSB_UIRQ_OOM_REPLY 2 ++#define PSB_UIRQ_FIRE_TA_REPLY 3 ++#define PSB_UIRQ_FIRE_RASTER_REPLY 4 ++ ++#define PSB_2D_SIZE (256*1024*1024) ++#define PSB_MAX_RELOC_PAGES 1024 ++ ++#define PSB_LOW_REG_OFFS 0x0204 ++#define PSB_HIGH_REG_OFFS 0x0600 ++ ++#define PSB_NUM_VBLANKS 2 ++ ++#define PSB_COMM_2D (PSB_ENGINE_2D << 4) ++#define PSB_COMM_3D (PSB_ENGINE_3D << 4) ++#define PSB_COMM_TA (PSB_ENGINE_TA << 4) ++#define PSB_COMM_HP (PSB_ENGINE_HP << 4) ++#define PSB_COMM_FW (2048 >> 2) ++ ++#define PSB_2D_SIZE (256*1024*1024) ++#define PSB_MAX_RELOC_PAGES 1024 ++ ++#define PSB_LOW_REG_OFFS 0x0204 ++#define PSB_HIGH_REG_OFFS 0x0600 ++ ++#define PSB_NUM_VBLANKS 2 ++#define PSB_WATCHDOG_DELAY (DRM_HZ / 10) ++ ++/* ++ * User options. ++ */ ++ ++struct drm_psb_uopt { ++ int disable_clock_gating; ++}; ++ ++struct psb_gtt { ++ struct drm_device *dev; ++ int initialized; ++ uint32_t gatt_start; ++ uint32_t gtt_start; ++ uint32_t gtt_phys_start; ++ unsigned gtt_pages; ++ unsigned gatt_pages; ++ uint32_t stolen_base; ++ uint32_t pge_ctl; ++ u16 gmch_ctrl; ++ unsigned long stolen_size; ++ uint32_t *gtt_map; ++ struct rw_semaphore sem; ++}; ++ ++struct psb_use_base { ++ struct list_head head; ++ struct drm_fence_object *fence; ++ unsigned int reg; ++ unsigned long offset; ++ unsigned int dm; ++}; ++ ++struct psb_buflist_item { ++ struct drm_buffer_object *bo; ++ void __user *data; ++ struct drm_bo_info_rep rep; ++ int ret; ++}; ++ ++struct psb_msvdx_cmd_queue { ++ struct list_head head; ++ void *cmd; ++ unsigned long cmd_size; ++ uint32_t sequence; ++}; ++ ++struct drm_psb_private { ++ unsigned long chipset; ++ ++ struct psb_xhw_buf resume_buf; ++ struct drm_psb_dev_info_arg dev_info; ++ struct drm_psb_uopt uopt; ++ ++ struct psb_gtt *pg; ++ ++ struct page *scratch_page; ++ struct page *comm_page; ++ ++ volatile uint32_t *comm; ++ uint32_t comm_mmu_offset; ++ uint32_t mmu_2d_offset; ++ uint32_t sequence[PSB_NUM_ENGINES]; ++ uint32_t last_sequence[PSB_NUM_ENGINES]; ++ int idle[PSB_NUM_ENGINES]; ++ uint32_t last_submitted_seq[PSB_NUM_ENGINES]; ++ int engine_lockup_2d; ++ ++ struct psb_mmu_driver *mmu; ++ struct psb_mmu_pd *pf_pd; ++ ++ uint8_t *sgx_reg; ++ uint8_t *vdc_reg; ++ uint8_t *msvdx_reg; ++ /*MSVDX*/ int msvdx_needs_reset; ++ int has_msvdx; ++ uint32_t gatt_free_offset; ++ ++ /* ++ * Fencing / irq. ++ */ ++ ++ uint32_t sgx_irq_mask; ++ uint32_t vdc_irq_mask; ++ ++ spinlock_t irqmask_lock; ++ spinlock_t sequence_lock; ++ int fence0_irq_on; ++ int irq_enabled; ++ unsigned int irqen_count_2d; ++ wait_queue_head_t event_2d_queue; ++ ++ uint32_t msvdx_current_sequence; ++ uint32_t msvdx_last_sequence; ++ int fence2_irq_on; ++ struct mutex mutex_2d; ++ ++ /* ++ * MSVDX Rendec Memory ++ */ ++ struct drm_buffer_object *ccb0; ++ uint32_t base_addr0; ++ struct drm_buffer_object *ccb1; ++ uint32_t base_addr1; ++ ++ /* ++ * Memory managers ++ */ ++ ++ int have_vram; ++ int have_tt; ++ int have_mem_mmu; ++ int have_mem_aper; ++ int have_mem_kernel; ++ int have_mem_pds; ++ int have_mem_rastgeom; ++ struct mutex temp_mem; ++ ++ /* ++ * Relocation buffer mapping. ++ */ ++ ++ spinlock_t reloc_lock; ++ unsigned int rel_mapped_pages; ++ wait_queue_head_t rel_mapped_queue; ++ ++ /* ++ * SAREA ++ */ ++ struct drm_psb_sarea *sarea_priv; ++ ++ /* ++ * LVDS info ++ */ ++ uint8_t blc_type; ++ uint8_t blc_pol; ++ uint8_t blc_freq; ++ uint8_t blc_minbrightness; ++ uint8_t blc_i2caddr; ++ uint8_t blc_brightnesscmd; ++ int backlight; /* restore backlight to this value */ ++ ++ struct intel_i2c_chan *i2c_bus; ++ u32 CoreClock; ++ u32 PWMControlRegFreq; ++ ++ unsigned char * OpRegion; ++ unsigned int OpRegionSize; ++ ++ int backlight_duty_cycle; /* restore backlight to this value */ ++ bool panel_wants_dither; ++ struct drm_display_mode *panel_fixed_mode; ++ ++ /* ++ * Register state ++ */ ++ uint32_t saveDSPACNTR; ++ uint32_t saveDSPBCNTR; ++ uint32_t savePIPEACONF; ++ uint32_t savePIPEBCONF; ++ uint32_t savePIPEASRC; ++ uint32_t savePIPEBSRC; ++ uint32_t saveFPA0; ++ uint32_t saveFPA1; ++ uint32_t saveDPLL_A; ++ uint32_t saveDPLL_A_MD; ++ uint32_t saveHTOTAL_A; ++ uint32_t saveHBLANK_A; ++ uint32_t saveHSYNC_A; ++ uint32_t saveVTOTAL_A; ++ uint32_t saveVBLANK_A; ++ uint32_t saveVSYNC_A; ++ uint32_t saveDSPASTRIDE; ++ uint32_t saveDSPASIZE; ++ uint32_t saveDSPAPOS; ++ uint32_t saveDSPABASE; ++ uint32_t saveDSPASURF; ++ uint32_t saveFPB0; ++ uint32_t saveFPB1; ++ uint32_t saveDPLL_B; ++ uint32_t saveDPLL_B_MD; ++ uint32_t saveHTOTAL_B; ++ uint32_t saveHBLANK_B; ++ uint32_t saveHSYNC_B; ++ uint32_t saveVTOTAL_B; ++ uint32_t saveVBLANK_B; ++ uint32_t saveVSYNC_B; ++ uint32_t saveDSPBSTRIDE; ++ uint32_t saveDSPBSIZE; ++ uint32_t saveDSPBPOS; ++ uint32_t saveDSPBBASE; ++ uint32_t saveDSPBSURF; ++ uint32_t saveVCLK_DIVISOR_VGA0; ++ uint32_t saveVCLK_DIVISOR_VGA1; ++ uint32_t saveVCLK_POST_DIV; ++ uint32_t saveVGACNTRL; ++ uint32_t saveADPA; ++ uint32_t saveLVDS; ++ uint32_t saveDVOA; ++ uint32_t saveDVOB; ++ uint32_t saveDVOC; ++ uint32_t savePP_ON; ++ uint32_t savePP_OFF; ++ uint32_t savePP_CONTROL; ++ uint32_t savePP_CYCLE; ++ uint32_t savePFIT_CONTROL; ++ uint32_t savePaletteA[256]; ++ uint32_t savePaletteB[256]; ++ uint32_t saveBLC_PWM_CTL; ++ ++ /* ++ * USE code base register management. ++ */ ++ ++ struct drm_reg_manager use_manager; ++ ++ /* ++ * Xhw ++ */ ++ ++ uint32_t *xhw; ++ struct drm_buffer_object *xhw_bo; ++ struct drm_bo_kmap_obj xhw_kmap; ++ struct list_head xhw_in; ++ spinlock_t xhw_lock; ++ atomic_t xhw_client; ++ struct drm_file *xhw_file; ++ wait_queue_head_t xhw_queue; ++ wait_queue_head_t xhw_caller_queue; ++ struct mutex xhw_mutex; ++ struct psb_xhw_buf *xhw_cur_buf; ++ int xhw_submit_ok; ++ int xhw_on; ++ ++ /* ++ * Scheduling. ++ */ ++ ++ struct mutex reset_mutex; ++ struct mutex cmdbuf_mutex; ++ struct psb_scheduler scheduler; ++ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS]; ++ uint32_t ta_mem_pages; ++ struct psb_ta_mem *ta_mem; ++ int force_ta_mem_load; ++ ++ /* ++ * Watchdog ++ */ ++ ++ spinlock_t watchdog_lock; ++ struct timer_list watchdog_timer; ++ struct work_struct watchdog_wq; ++ struct work_struct msvdx_watchdog_wq; ++ int timer_available; ++ ++ /* ++ * msvdx command queue ++ */ ++ spinlock_t msvdx_lock; ++ struct mutex msvdx_mutex; ++ struct list_head msvdx_queue; ++ int msvdx_busy; ++}; ++ ++struct psb_mmu_driver; ++ ++extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers, ++ int trap_pagefaults, ++ int invalid_type); ++extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver); ++extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver); ++extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset, ++ uint32_t gtt_start, uint32_t gtt_pages); ++extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset); ++extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver, ++ int trap_pagefaults, ++ int invalid_type); ++extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd); ++extern void psb_mmu_flush(struct psb_mmu_driver *driver); ++extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd, ++ unsigned long address, ++ uint32_t num_pages); ++extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, ++ uint32_t start_pfn, ++ unsigned long address, ++ uint32_t num_pages, int type); ++extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, ++ unsigned long *pfn); ++ ++/* ++ * Enable / disable MMU for different requestors. ++ */ ++ ++extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver, ++ uint32_t mask); ++extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver, ++ uint32_t mask); ++extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context); ++extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages, ++ unsigned long address, uint32_t num_pages, ++ uint32_t desired_tile_stride, ++ uint32_t hw_tile_stride, int type); ++extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address, ++ uint32_t num_pages, ++ uint32_t desired_tile_stride, ++ uint32_t hw_tile_stride); ++/* ++ * psb_sgx.c ++ */ ++ ++extern int psb_blit_sequence(struct drm_psb_private *dev_priv, ++ uint32_t sequence); ++extern void psb_init_2d(struct drm_psb_private *dev_priv); ++extern int drm_psb_idle(struct drm_device *dev); ++extern int psb_emit_2d_copy_blit(struct drm_device *dev, ++ uint32_t src_offset, ++ uint32_t dst_offset, uint32_t pages, ++ int direction); ++extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs, ++ unsigned int cmds); ++extern int psb_submit_copy_cmdbuf(struct drm_device *dev, ++ struct drm_buffer_object *cmd_buffer, ++ unsigned long cmd_offset, ++ unsigned long cmd_size, int engine, ++ uint32_t * copy_buffer); ++ ++extern int psb_fence_for_errors(struct drm_file *priv, ++ struct drm_psb_cmdbuf_arg *arg, ++ struct drm_fence_arg *fence_arg, ++ struct drm_fence_object **fence_p); ++ ++/* ++ * psb_irq.c ++ */ ++ ++extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS); ++extern void psb_irq_preinstall(struct drm_device *dev); ++extern void psb_irq_postinstall(struct drm_device *dev); ++extern void psb_irq_uninstall(struct drm_device *dev); ++extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); ++extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); ++ ++/* ++ * psb_fence.c ++ */ ++ ++extern void psb_poke_flush(struct drm_device *dev, uint32_t class); ++extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class, ++ uint32_t flags, uint32_t * sequence, ++ uint32_t * native_type); ++extern void psb_fence_handler(struct drm_device *dev, uint32_t class); ++extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class, ++ uint32_t flags); ++extern void psb_2D_irq_off(struct drm_psb_private *dev_priv); ++extern void psb_2D_irq_on(struct drm_psb_private *dev_priv); ++extern uint32_t psb_fence_advance_sequence(struct drm_device *dev, ++ uint32_t class); ++extern void psb_fence_error(struct drm_device *dev, ++ uint32_t class, ++ uint32_t sequence, uint32_t type, int error); ++ ++/*MSVDX stuff*/ ++extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv); ++extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv); ++ ++/* ++ * psb_buffer.c ++ */ ++extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev); ++extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class, ++ uint32_t * type); ++extern uint32_t psb_evict_mask(struct drm_buffer_object *bo); ++extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags); ++extern int psb_init_mem_type(struct drm_device *dev, uint32_t type, ++ struct drm_mem_type_manager *man); ++extern int psb_move(struct drm_buffer_object *bo, ++ int evict, int no_wait, struct drm_bo_mem_reg *new_mem); ++ ++/* ++ * psb_gtt.c ++ */ ++extern int psb_gtt_init(struct psb_gtt *pg, int resume); ++extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages, ++ unsigned offset_pages, unsigned num_pages, ++ unsigned desired_tile_stride, ++ unsigned hw_tile_stride, int type); ++extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages, ++ unsigned num_pages, ++ unsigned desired_tile_stride, ++ unsigned hw_tile_stride); ++ ++extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev); ++extern void psb_gtt_takedown(struct psb_gtt *pg, int free); ++ ++/* ++ * psb_fb.c ++ */ ++extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc); ++extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc); ++extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++ ++/* ++ * psb_reset.c ++ */ ++ ++extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d); ++extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv); ++extern void psb_watchdog_init(struct drm_psb_private *dev_priv); ++extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv); ++ ++/* ++ * psb_regman.c ++ */ ++ ++extern void psb_takedown_use_base(struct drm_psb_private *dev_priv); ++extern int psb_grab_use_base(struct drm_psb_private *dev_priv, ++ unsigned long dev_virtual, ++ unsigned long size, ++ unsigned int data_master, ++ uint32_t fence_class, ++ uint32_t fence_type, ++ int no_wait, ++ int ignore_signals, ++ int *r_reg, uint32_t * r_offset); ++extern int psb_init_use_base(struct drm_psb_private *dev_priv, ++ unsigned int reg_start, unsigned int reg_num); ++ ++/* ++ * psb_xhw.c ++ */ ++ ++extern int psb_xhw_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *file_priv); ++extern int psb_xhw_init(struct drm_device *dev); ++extern void psb_xhw_takedown(struct drm_psb_private *dev_priv); ++extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv, ++ struct drm_file *file_priv, int closing); ++extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, ++ uint32_t fire_flags, ++ uint32_t hw_context, ++ uint32_t * cookie, ++ uint32_t * oom_cmds, ++ uint32_t num_oom_cmds, ++ uint32_t offset, ++ uint32_t engine, uint32_t flags); ++extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, uint32_t fire_flags); ++extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, ++ uint32_t w, ++ uint32_t h, ++ uint32_t * hw_cookie, ++ uint32_t * bo_size, ++ uint32_t * clear_p_start, ++ uint32_t * clear_num_pages); ++ ++extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf); ++extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, ++ uint32_t pages, ++ uint32_t * hw_cookie, uint32_t * size); ++extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, uint32_t * cookie); ++extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, ++ uint32_t * cookie, ++ uint32_t * bca, ++ uint32_t * rca, uint32_t * flags); ++extern int psb_xhw_vistest(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf); ++extern int psb_xhw_handler(struct drm_psb_private *dev_priv); ++extern int psb_xhw_resume(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf); ++extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, uint32_t * cookie); ++extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf, ++ uint32_t flags, ++ uint32_t param_offset, ++ uint32_t pt_offset, ++ uint32_t *hw_cookie); ++extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv, ++ struct psb_xhw_buf *buf); ++ ++/* ++ * Utilities ++ */ ++ ++#define PSB_ALIGN_TO(_val, _align) \ ++ (((_val) + ((_align) - 1)) & ~((_align) - 1)) ++#define PSB_WVDC32(_val, _offs) \ ++ iowrite32(_val, dev_priv->vdc_reg + (_offs)) ++#define PSB_RVDC32(_offs) \ ++ ioread32(dev_priv->vdc_reg + (_offs)) ++#define PSB_WSGX32(_val, _offs) \ ++ iowrite32(_val, dev_priv->sgx_reg + (_offs)) ++#define PSB_RSGX32(_offs) \ ++ ioread32(dev_priv->sgx_reg + (_offs)) ++#define PSB_WMSVDX32(_val, _offs) \ ++ iowrite32(_val, dev_priv->msvdx_reg + (_offs)) ++#define PSB_RMSVDX32(_offs) \ ++ ioread32(dev_priv->msvdx_reg + (_offs)) ++ ++#define PSB_ALPL(_val, _base) \ ++ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) ++#define PSB_ALPLM(_val, _base) \ ++ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK)) ++ ++static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b) ++{ ++ s64 tmp; ++ s64 a64 = (s64) a; ++ s64 b64 = (s64) b; ++ ++ tmp = a64 * b64; ++ return tmp / (1ULL << PSB_FIXED_SHIFT) + ++ ((tmp & 0x80000000ULL) ? 1 : 0); ++} ++ ++static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b) ++{ ++ u64 tmp; ++ u64 a64 = (u64) a; ++ u64 b64 = (u64) b; ++ ++ tmp = a64 * b64; ++ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0); ++} ++ ++static inline uint32_t psb_ufixed_to_float32(psb_ufixed a) ++{ ++ uint32_t exp = 0x7f + 7; ++ uint32_t mantissa = (uint32_t) a; ++ ++ if (a == 0) ++ return 0; ++ while ((mantissa & 0xff800000) == 0) { ++ exp -= 1; ++ mantissa <<= 1; ++ } ++ while ((mantissa & 0xff800000) > 0x00800000) { ++ exp += 1; ++ mantissa >>= 1; ++ } ++ return (mantissa & ~0xff800000) | (exp << 23); ++} ++ ++static inline uint32_t psb_fixed_to_float32(psb_fixed a) ++{ ++ if (a < 0) ++ return psb_ufixed_to_float32(-a) | 0x80000000; ++ else ++ return psb_ufixed_to_float32(a); ++} ++ ++#define PSB_D_RENDER (1 << 16) ++ ++#define PSB_D_GENERAL (1 << 0) ++#define PSB_D_INIT (1 << 1) ++#define PSB_D_IRQ (1 << 2) ++#define PSB_D_FW (1 << 3) ++#define PSB_D_PERF (1 << 4) ++#define PSB_D_TMP (1 << 5) ++ ++extern int drm_psb_debug; ++extern int drm_psb_no_fb; ++extern int drm_psb_disable_vsync; ++ ++#define PSB_DEBUG_FW(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg) ++#define PSB_DEBUG_GENERAL(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg) ++#define PSB_DEBUG_INIT(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg) ++#define PSB_DEBUG_IRQ(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg) ++#define PSB_DEBUG_RENDER(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg) ++#define PSB_DEBUG_PERF(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg) ++#define PSB_DEBUG_TMP(_fmt, _arg...) \ ++ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg) ++ ++#if DRM_DEBUG_CODE ++#define PSB_DEBUG(_flag, _fmt, _arg...) \ ++ do { \ ++ if ((_flag) & drm_psb_debug) \ ++ printk(KERN_DEBUG \ ++ "[psb:0x%02x:%s] " _fmt , _flag, \ ++ __FUNCTION__ , ##_arg); \ ++ } while (0) ++#else ++#define PSB_DEBUG(_fmt, _arg...) do { } while (0) ++#endif ++ ++#endif +Index: libdrm-2.4.4/shared-core/psb_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ libdrm-2.4.4/shared-core/psb_reg.h 2009-02-04 16:39:55.000000000 +0000 +@@ -0,0 +1,555 @@ ++/************************************************************************** ++ * ++ * Copyright (c) (2005-2007) Imagination Technologies Limited. ++ * Copyright (c) 2007, Intel Corporation. ++ * All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to ++ * develop this driver. ++ * ++ **************************************************************************/ ++/* ++ */ ++#ifndef _PSB_REG_H_ ++#define _PSB_REG_H_ ++ ++#define PSB_CR_CLKGATECTL 0x0000 ++#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24) ++#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20) ++#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20) ++#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16) ++#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16) ++#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12) ++#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12) ++#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8) ++#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8) ++#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4) ++#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4) ++#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0) ++#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0) ++#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0) ++#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1) ++#define _PSB_C_CLKGATECTL_CLKG_AUTO (2) ++ ++#define PSB_CR_CORE_ID 0x0010 ++#define _PSB_CC_ID_ID_SHIFT (16) ++#define _PSB_CC_ID_ID_MASK (0xFFFF << 16) ++#define _PSB_CC_ID_CONFIG_SHIFT (0) ++#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0) ++ ++#define PSB_CR_CORE_REVISION 0x0014 ++#define _PSB_CC_REVISION_DESIGNER_SHIFT (24) ++#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24) ++#define _PSB_CC_REVISION_MAJOR_SHIFT (16) ++#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16) ++#define _PSB_CC_REVISION_MINOR_SHIFT (8) ++#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8) ++#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0) ++#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0) ++ ++#define PSB_CR_DESIGNER_REV_FIELD1 0x0018 ++ ++#define PSB_CR_SOFT_RESET 0x0080 ++#define _PSB_CS_RESET_TSP_RESET (1 << 6) ++#define _PSB_CS_RESET_ISP_RESET (1 << 5) ++#define _PSB_CS_RESET_USE_RESET (1 << 4) ++#define _PSB_CS_RESET_TA_RESET (1 << 3) ++#define _PSB_CS_RESET_DPM_RESET (1 << 2) ++#define _PSB_CS_RESET_TWOD_RESET (1 << 1) ++#define _PSB_CS_RESET_BIF_RESET (1 << 0) ++ ++#define PSB_CR_DESIGNER_REV_FIELD2 0x001C ++ ++#define PSB_CR_EVENT_STATUS 0x012C ++ ++#define PSB_CR_EVENT_HOST_ENABLE 0x0130 ++ ++#define PSB_CR_EVENT_HOST_CLEAR 0x0134 ++#define _PSB_CE_MASTER_INTERRUPT (1 << 31) ++#define _PSB_CE_TA_DPM_FAULT (1 << 28) ++#define _PSB_CE_TWOD_COMPLETE (1 << 27) ++#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25) ++#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24) ++#define _PSB_CE_PIXELBE_END_RENDER (1 << 18) ++#define _PSB_CE_SW_EVENT (1 << 14) ++#define _PSB_CE_TA_FINISHED (1 << 13) ++#define _PSB_CE_TA_TERMINATE (1 << 12) ++#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3) ++#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2) ++#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1) ++#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0) ++ ++ ++#define PSB_USE_OFFSET_MASK 0x0007FFFF ++#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1) ++#define PSB_CR_USE_CODE_BASE0 0x0A0C ++#define PSB_CR_USE_CODE_BASE1 0x0A10 ++#define PSB_CR_USE_CODE_BASE2 0x0A14 ++#define PSB_CR_USE_CODE_BASE3 0x0A18 ++#define PSB_CR_USE_CODE_BASE4 0x0A1C ++#define PSB_CR_USE_CODE_BASE5 0x0A20 ++#define PSB_CR_USE_CODE_BASE6 0x0A24 ++#define PSB_CR_USE_CODE_BASE7 0x0A28 ++#define PSB_CR_USE_CODE_BASE8 0x0A2C ++#define PSB_CR_USE_CODE_BASE9 0x0A30 ++#define PSB_CR_USE_CODE_BASE10 0x0A34 ++#define PSB_CR_USE_CODE_BASE11 0x0A38 ++#define PSB_CR_USE_CODE_BASE12 0x0A3C ++#define PSB_CR_USE_CODE_BASE13 0x0A40 ++#define PSB_CR_USE_CODE_BASE14 0x0A44 ++#define PSB_CR_USE_CODE_BASE15 0x0A48 ++#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2)) ++#define _PSB_CUC_BASE_DM_SHIFT (25) ++#define _PSB_CUC_BASE_DM_MASK (0x3 << 25) ++#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address? ++#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7) ++#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0) ++#define _PSB_CUC_DM_VERTEX (0) ++#define _PSB_CUC_DM_PIXEL (1) ++#define _PSB_CUC_DM_RESERVED (2) ++#define _PSB_CUC_DM_EDM (3) ++ ++#define PSB_CR_PDS_EXEC_BASE 0x0AB8 ++#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address ++#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20) ++ ++#define PSB_CR_EVENT_KICKER 0x0AC4 ++#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address ++ ++#define PSB_CR_EVENT_KICK 0x0AC8 ++#define _PSB_CE_KICK_NOW (1 << 0) ++ ++ ++#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38 ++ ++#define PSB_CR_BIF_CTRL 0x0C00 ++#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4) ++#define _PSB_CB_CTRL_INVALDC (1 << 3) ++#define _PSB_CB_CTRL_FLUSH (1 << 2) ++ ++#define PSB_CR_BIF_INT_STAT 0x0C04 ++ ++#define PSB_CR_BIF_FAULT 0x0C08 ++#define _PSB_CBI_STAT_PF_N_RW (1 << 14) ++#define _PSB_CBI_STAT_FAULT_SHIFT (0) ++#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0) ++#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1) ++#define _PSB_CBI_STAT_FAULT_TA (1 << 2) ++#define _PSB_CBI_STAT_FAULT_VDM (1 << 3) ++#define _PSB_CBI_STAT_FAULT_2D (1 << 4) ++#define _PSB_CBI_STAT_FAULT_PBE (1 << 5) ++#define _PSB_CBI_STAT_FAULT_TSP (1 << 6) ++#define _PSB_CBI_STAT_FAULT_ISP (1 << 7) ++#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8) ++#define _PSB_CBI_STAT_FAULT_HOST (1 << 9) ++ ++#define PSB_CR_BIF_BANK0 0x0C78 ++ ++#define PSB_CR_BIF_BANK1 0x0C7C ++ ++#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84 ++ ++#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88 ++#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC ++ ++#define PSB_CR_2D_SOCIF 0x0E18 ++#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0) ++#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0) ++#define _PSB_C2_SOCIF_EMPTY (0x80 << 0) ++ ++#define PSB_CR_2D_BLIT_STATUS 0x0E04 ++#define _PSB_C2B_STATUS_BUSY (1 << 24) ++#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0) ++#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0) ++ ++/* ++ * 2D defs. ++ */ ++ ++/* ++ * 2D Slave Port Data : Block Header's Object Type ++ */ ++ ++#define PSB_2D_CLIP_BH (0x00000000) ++#define PSB_2D_PAT_BH (0x10000000) ++#define PSB_2D_CTRL_BH (0x20000000) ++#define PSB_2D_SRC_OFF_BH (0x30000000) ++#define PSB_2D_MASK_OFF_BH (0x40000000) ++#define PSB_2D_RESERVED1_BH (0x50000000) ++#define PSB_2D_RESERVED2_BH (0x60000000) ++#define PSB_2D_FENCE_BH (0x70000000) ++#define PSB_2D_BLIT_BH (0x80000000) ++#define PSB_2D_SRC_SURF_BH (0x90000000) ++#define PSB_2D_DST_SURF_BH (0xA0000000) ++#define PSB_2D_PAT_SURF_BH (0xB0000000) ++#define PSB_2D_SRC_PAL_BH (0xC0000000) ++#define PSB_2D_PAT_PAL_BH (0xD0000000) ++#define PSB_2D_MASK_SURF_BH (0xE0000000) ++#define PSB_2D_FLUSH_BH (0xF0000000) ++ ++/* ++ * Clip Definition block (PSB_2D_CLIP_BH) ++ */ ++#define PSB_2D_CLIPCOUNT_MAX (1) ++#define PSB_2D_CLIPCOUNT_MASK (0x00000000) ++#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF) ++#define PSB_2D_CLIPCOUNT_SHIFT (0) ++// clip rectangle min & max ++#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000) ++#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF) ++#define PSB_2D_CLIP_XMAX_SHIFT (12) ++#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF) ++#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000) ++#define PSB_2D_CLIP_XMIN_SHIFT (0) ++// clip rectangle offset ++#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000) ++#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF) ++#define PSB_2D_CLIP_YMAX_SHIFT (12) ++#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF) ++#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000) ++#define PSB_2D_CLIP_YMIN_SHIFT (0) ++ ++/* ++ * Pattern Control (PSB_2D_PAT_BH) ++ */ ++#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F) ++#define PSB_2D_PAT_HEIGHT_SHIFT (0) ++#define PSB_2D_PAT_WIDTH_MASK (0x000003E0) ++#define PSB_2D_PAT_WIDTH_SHIFT (5) ++#define PSB_2D_PAT_YSTART_MASK (0x00007C00) ++#define PSB_2D_PAT_YSTART_SHIFT (10) ++#define PSB_2D_PAT_XSTART_MASK (0x000F8000) ++#define PSB_2D_PAT_XSTART_SHIFT (15) ++ ++/* ++ * 2D Control block (PSB_2D_CTRL_BH) ++ */ ++// Present Flags ++#define PSB_2D_SRCCK_CTRL (0x00000001) ++#define PSB_2D_DSTCK_CTRL (0x00000002) ++#define PSB_2D_ALPHA_CTRL (0x00000004) ++// Colour Key Colour (SRC/DST) ++#define PSB_2D_CK_COL_MASK (0xFFFFFFFF) ++#define PSB_2D_CK_COL_CLRMASK (0x00000000) ++#define PSB_2D_CK_COL_SHIFT (0) ++// Colour Key Mask (SRC/DST) ++#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF) ++#define PSB_2D_CK_MASK_CLRMASK (0x00000000) ++#define PSB_2D_CK_MASK_SHIFT (0) ++// Alpha Control (Alpha/RGB) ++#define PSB_2D_GBLALPHA_MASK (0x000FF000) ++#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF) ++#define PSB_2D_GBLALPHA_SHIFT (12) ++#define PSB_2D_SRCALPHA_OP_MASK (0x00700000) ++#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF) ++#define PSB_2D_SRCALPHA_OP_SHIFT (20) ++#define PSB_2D_SRCALPHA_OP_ONE (0x00000000) ++#define PSB_2D_SRCALPHA_OP_SRC (0x00100000) ++#define PSB_2D_SRCALPHA_OP_DST (0x00200000) ++#define PSB_2D_SRCALPHA_OP_SG (0x00300000) ++#define PSB_2D_SRCALPHA_OP_DG (0x00400000) ++#define PSB_2D_SRCALPHA_OP_GBL (0x00500000) ++#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000) ++#define PSB_2D_SRCALPHA_INVERT (0x00800000) ++#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF) ++#define PSB_2D_DSTALPHA_OP_MASK (0x07000000) ++#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF) ++#define PSB_2D_DSTALPHA_OP_SHIFT (24) ++#define PSB_2D_DSTALPHA_OP_ONE (0x00000000) ++#define PSB_2D_DSTALPHA_OP_SRC (0x01000000) ++#define PSB_2D_DSTALPHA_OP_DST (0x02000000) ++#define PSB_2D_DSTALPHA_OP_SG (0x03000000) ++#define PSB_2D_DSTALPHA_OP_DG (0x04000000) ++#define PSB_2D_DSTALPHA_OP_GBL (0x05000000) ++#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000) ++#define PSB_2D_DSTALPHA_INVERT (0x08000000) ++#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF) ++ ++#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000) ++#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF) ++#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000) ++#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF) ++ ++/* ++ *Source Offset (PSB_2D_SRC_OFF_BH) ++ */ ++#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12) ++#define PSB_2D_SRCOFF_XSTART_SHIFT (12) ++#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF) ++#define PSB_2D_SRCOFF_YSTART_SHIFT (0) ++ ++/* ++ * Mask Offset (PSB_2D_MASK_OFF_BH) ++ */ ++#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12) ++#define PSB_2D_MASKOFF_XSTART_SHIFT (12) ++#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF) ++#define PSB_2D_MASKOFF_YSTART_SHIFT (0) ++ ++/* ++ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored ++ */ ++ ++/* ++ *Blit Rectangle (PSB_2D_BLIT_BH) ++ */ ++ ++#define PSB_2D_ROT_MASK (3<<25) ++#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK) ++#define PSB_2D_ROT_NONE (0<<25) ++#define PSB_2D_ROT_90DEGS (1<<25) ++#define PSB_2D_ROT_180DEGS (2<<25) ++#define PSB_2D_ROT_270DEGS (3<<25) ++ ++#define PSB_2D_COPYORDER_MASK (3<<23) ++#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK) ++#define PSB_2D_COPYORDER_TL2BR (0<<23) ++#define PSB_2D_COPYORDER_BR2TL (1<<23) ++#define PSB_2D_COPYORDER_TR2BL (2<<23) ++#define PSB_2D_COPYORDER_BL2TR (3<<23) ++ ++#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF) ++#define PSB_2D_DSTCK_DISABLE (0x00000000) ++#define PSB_2D_DSTCK_PASS (0x00200000) ++#define PSB_2D_DSTCK_REJECT (0x00400000) ++ ++#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF) ++#define PSB_2D_SRCCK_DISABLE (0x00000000) ++#define PSB_2D_SRCCK_PASS (0x00080000) ++#define PSB_2D_SRCCK_REJECT (0x00100000) ++ ++#define PSB_2D_CLIP_ENABLE (0x00040000) ++ ++#define PSB_2D_ALPHA_ENABLE (0x00020000) ++ ++#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF) ++#define PSB_2D_PAT_MASK (0x00010000) ++#define PSB_2D_USE_PAT (0x00010000) ++#define PSB_2D_USE_FILL (0x00000000) ++/* ++ * Tungsten Graphics note on rop codes: If rop A and rop B are ++ * identical, the mask surface will not be read and need not be ++ * set up. ++ */ ++ ++#define PSB_2D_ROP3B_MASK (0x0000FF00) ++#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF) ++#define PSB_2D_ROP3B_SHIFT (8) ++// rop code A ++#define PSB_2D_ROP3A_MASK (0x000000FF) ++#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00) ++#define PSB_2D_ROP3A_SHIFT (0) ++ ++#define PSB_2D_ROP4_MASK (0x0000FFFF) ++/* ++ * DWORD0: (Only pass if Pattern control == Use Fill Colour) ++ * Fill Colour RGBA8888 ++ */ ++#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF) ++#define PSB_2D_FILLCOLOUR_SHIFT (0) ++/* ++ * DWORD1: (Always Present) ++ * X Start (Dest) ++ * Y Start (Dest) ++ */ ++#define PSB_2D_DST_XSTART_MASK (0x00FFF000) ++#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF) ++#define PSB_2D_DST_XSTART_SHIFT (12) ++#define PSB_2D_DST_YSTART_MASK (0x00000FFF) ++#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000) ++#define PSB_2D_DST_YSTART_SHIFT (0) ++/* ++ * DWORD2: (Always Present) ++ * X Size (Dest) ++ * Y Size (Dest) ++ */ ++#define PSB_2D_DST_XSIZE_MASK (0x00FFF000) ++#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF) ++#define PSB_2D_DST_XSIZE_SHIFT (12) ++#define PSB_2D_DST_YSIZE_MASK (0x00000FFF) ++#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000) ++#define PSB_2D_DST_YSIZE_SHIFT (0) ++ ++/* ++ * Source Surface (PSB_2D_SRC_SURF_BH) ++ */ ++/* ++ * WORD 0 ++ */ ++ ++#define PSB_2D_SRC_FORMAT_MASK (0x00078000) ++#define PSB_2D_SRC_1_PAL (0x00000000) ++#define PSB_2D_SRC_2_PAL (0x00008000) ++#define PSB_2D_SRC_4_PAL (0x00010000) ++#define PSB_2D_SRC_8_PAL (0x00018000) ++#define PSB_2D_SRC_8_ALPHA (0x00020000) ++#define PSB_2D_SRC_4_ALPHA (0x00028000) ++#define PSB_2D_SRC_332RGB (0x00030000) ++#define PSB_2D_SRC_4444ARGB (0x00038000) ++#define PSB_2D_SRC_555RGB (0x00040000) ++#define PSB_2D_SRC_1555ARGB (0x00048000) ++#define PSB_2D_SRC_565RGB (0x00050000) ++#define PSB_2D_SRC_0888ARGB (0x00058000) ++#define PSB_2D_SRC_8888ARGB (0x00060000) ++#define PSB_2D_SRC_8888UYVY (0x00068000) ++#define PSB_2D_SRC_RESERVED (0x00070000) ++#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000) ++ ++ ++#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF) ++#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000) ++#define PSB_2D_SRC_STRIDE_SHIFT (0) ++/* ++ * WORD 1 - Base Address ++ */ ++#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC) ++#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003) ++#define PSB_2D_SRC_ADDR_SHIFT (2) ++#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2) ++ ++/* ++ * Pattern Surface (PSB_2D_PAT_SURF_BH) ++ */ ++/* ++ * WORD 0 ++ */ ++ ++#define PSB_2D_PAT_FORMAT_MASK (0x00078000) ++#define PSB_2D_PAT_1_PAL (0x00000000) ++#define PSB_2D_PAT_2_PAL (0x00008000) ++#define PSB_2D_PAT_4_PAL (0x00010000) ++#define PSB_2D_PAT_8_PAL (0x00018000) ++#define PSB_2D_PAT_8_ALPHA (0x00020000) ++#define PSB_2D_PAT_4_ALPHA (0x00028000) ++#define PSB_2D_PAT_332RGB (0x00030000) ++#define PSB_2D_PAT_4444ARGB (0x00038000) ++#define PSB_2D_PAT_555RGB (0x00040000) ++#define PSB_2D_PAT_1555ARGB (0x00048000) ++#define PSB_2D_PAT_565RGB (0x00050000) ++#define PSB_2D_PAT_0888ARGB (0x00058000) ++#define PSB_2D_PAT_8888ARGB (0x00060000) ++ ++#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF) ++#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000) ++#define PSB_2D_PAT_STRIDE_SHIFT (0) ++/* ++ * WORD 1 - Base Address ++ */ ++#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC) ++#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003) ++#define PSB_2D_PAT_ADDR_SHIFT (2) ++#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2) ++ ++/* ++ * Destination Surface (PSB_2D_DST_SURF_BH) ++ */ ++/* ++ * WORD 0 ++ */ ++ ++#define PSB_2D_DST_FORMAT_MASK (0x00078000) ++#define PSB_2D_DST_332RGB (0x00030000) ++#define PSB_2D_DST_4444ARGB (0x00038000) ++#define PSB_2D_DST_555RGB (0x00040000) ++#define PSB_2D_DST_1555ARGB (0x00048000) ++#define PSB_2D_DST_565RGB (0x00050000) ++#define PSB_2D_DST_0888ARGB (0x00058000) ++#define PSB_2D_DST_8888ARGB (0x00060000) ++#define PSB_2D_DST_8888AYUV (0x00070000) ++ ++#define PSB_2D_DST_STRIDE_MASK (0x00007FFF) ++#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000) ++#define PSB_2D_DST_STRIDE_SHIFT (0) ++/* ++ * WORD 1 - Base Address ++ */ ++#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC) ++#define PSB_2D_DST_ADDR_CLRMASK (0x00000003) ++#define PSB_2D_DST_ADDR_SHIFT (2) ++#define PSB_2D_DST_ADDR_ALIGNSHIFT (2) ++ ++/* ++ * Mask Surface (PSB_2D_MASK_SURF_BH) ++ */ ++/* ++ * WORD 0 ++ */ ++#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF) ++#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000) ++#define PSB_2D_MASK_STRIDE_SHIFT (0) ++/* ++ * WORD 1 - Base Address ++ */ ++#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC) ++#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003) ++#define PSB_2D_MASK_ADDR_SHIFT (2) ++#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2) ++ ++/* ++ * Source Palette (PSB_2D_SRC_PAL_BH) ++ */ ++ ++#define PSB_2D_SRCPAL_ADDR_SHIFT (0) ++#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007) ++#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8) ++#define PSB_2D_SRCPAL_BYTEALIGN (1024) ++ ++/* ++ * Pattern Palette (PSB_2D_PAT_PAL_BH) ++ */ ++ ++#define PSB_2D_PATPAL_ADDR_SHIFT (0) ++#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007) ++#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8) ++#define PSB_2D_PATPAL_BYTEALIGN (1024) ++ ++/* ++ * Rop3 Codes (2 LS bytes) ++ */ ++ ++#define PSB_2D_ROP3_SRCCOPY (0xCCCC) ++#define PSB_2D_ROP3_PATCOPY (0xF0F0) ++#define PSB_2D_ROP3_WHITENESS (0xFFFF) ++#define PSB_2D_ROP3_BLACKNESS (0x0000) ++#define PSB_2D_ROP3_SRC (0xCC) ++#define PSB_2D_ROP3_PAT (0xF0) ++#define PSB_2D_ROP3_DST (0xAA) ++ ++ ++/* ++ * Sizes. ++ */ ++ ++#define PSB_SCENE_HW_COOKIE_SIZE 16 ++#define PSB_TA_MEM_HW_COOKIE_SIZE 16 ++ ++/* ++ * Scene stuff. ++ */ ++ ++#define PSB_NUM_HW_SCENES 2 ++ ++/* ++ * Scheduler completion actions. ++ */ ++ ++#define PSB_RASTER_BLOCK 0 ++#define PSB_RASTER 1 ++#define PSB_RETURN 2 ++#define PSB_TA 3 ++ ++ ++#endif +Index: libdrm-2.4.4/shared-core/radeon_drm.h +=================================================================== +--- libdrm-2.4.4.orig/shared-core/radeon_drm.h 2008-10-09 20:02:11.000000000 +0100 ++++ libdrm-2.4.4/shared-core/radeon_drm.h 2009-02-04 16:39:55.000000000 +0000 +@@ -453,8 +453,17 @@ + int pfCurrentPage; /* which buffer is being displayed? */ + int crtc2_base; /* CRTC2 frame offset */ + int tiling_enabled; /* set by drm, read by 2d + 3d clients */ ++ ++ unsigned int last_fence; + } drm_radeon_sarea_t; + ++/* The only fence class we support */ ++#define DRM_RADEON_FENCE_CLASS_ACCEL 0 ++/* Fence type that guarantees read-write flush */ ++#define DRM_RADEON_FENCE_TYPE_RW 2 ++/* cache flushes programmed just before the fence */ ++#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 ++ + /* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmRadeon.h) + * +Index: libdrm-2.4.4/shared-core/tdfx_drv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ libdrm-2.4.4/shared-core/tdfx_drv.h 2009-02-04 16:39:55.000000000 +0000 +@@ -0,0 +1,47 @@ ++/* tdfx.h -- 3dfx DRM template customization -*- linux-c -*- ++ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com ++ */ ++/* ++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Gareth Hughes <gareth@valinux.com> ++ */ ++ ++#ifndef __TDFX_H__ ++#define __TDFX_H__ ++ ++/* General customization: ++ */ ++ ++#define DRIVER_AUTHOR "VA Linux Systems Inc." ++ ++#define DRIVER_NAME "tdfx" ++#define DRIVER_DESC "3dfx Banshee/Voodoo3+" ++#define DRIVER_DATE "20010216" ++ ++#define DRIVER_MAJOR 1 ++#define DRIVER_MINOR 0 ++#define DRIVER_PATCHLEVEL 0 ++ ++#endif +Index: libdrm-2.4.4/libdrm/Makefile.am +=================================================================== +--- libdrm-2.4.4.orig/libdrm/Makefile.am 2009-02-04 16:42:01.000000000 +0000 ++++ libdrm-2.4.4/libdrm/Makefile.am 2009-02-04 16:45:06.000000000 +0000 +@@ -31,6 +31,6 @@ + libdrm_lists.h + + libdrmincludedir = ${includedir} +-libdrminclude_HEADERS = xf86drm.h xf86drmMode.h ++libdrminclude_HEADERS = xf86drm.h xf86drmMode.h xf86mm.h libdrm_lists.h + + EXTRA_DIST = ChangeLog TODO diff --git a/meta/packages/drm/libdrm_2.4.4.bb b/meta/packages/drm/libdrm_2.4.4.bb index 29b3c4cbf..ddb3776ad 100644 --- a/meta/packages/drm/libdrm_2.4.4.bb +++ b/meta/packages/drm/libdrm_2.4.4.bb @@ -1,6 +1,8 @@ SECTION = "x11/base" LICENSE = "MIT" -SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2" +SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2 \ + file://poulsbo.patch;patch=1" +PR = "r2" PROVIDES = "drm" DEPENDS = "libpthread-stubs" |