o Using a bus for the memory input too.

o Adding a test case for reading data from RAM.

5 files changed, 87 insertions, 39 deletions

diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd
index 8cbff92..5f0329e 100644
--- a/vhdl/ice.vhd
+++ b/vhdl/ice.vhd
@@ -7,9 +7,7 @@ entity ice is
   port (
     mcu_in              : in mcu_in;
     bit_out             : out std_logic;
-    oe                  : in std_logic;
-    ce                  : in std_logic;
-    we                  : in std_logic
+    ram_in              : in ram_in
   );
 end ice;
 
@@ -25,8 +23,7 @@ begin
     bit_out,
     ah,
     al,
-    d,          -- d_out,
-    d           -- d_in
+    d
   );
 
   address : ram_address <= ah(14 downto 8) & al;
@@ -34,9 +31,9 @@ begin
   ram : entity work.as7c256a port map(
     address => ram_address,
     dataio => d,
-    oe_bar => oe,
-    ce_bar => ce,
-    we_bar => we
+    oe_bar => ram_in.oe,
+    ce_bar => ram_in.ce,
+    we_bar => ram_in.we
   );
 
 end;
diff --git a/vhdl/ice_tb.vhd b/vhdl/ice_tb.vhd
index dae94f4..c442f41 100644
--- a/vhdl/ice_tb.vhd
+++ b/vhdl/ice_tb.vhd
@@ -9,19 +9,26 @@ end;
 architecture behavior of ice_tb is
   signal mcu_in         : mcu_in;
   signal bit_out        : std_logic;
-  signal oe             : std_logic := disable;
-  signal ce             : std_logic := enable;
-  signal we             : std_logic := disable;
+  signal ram_in         : ram_in;
+  signal data           : std_logic_vector(7 downto 0);
 begin
   ice : entity work.ice port map(
-    mcu_in, bit_out, oe, ce, we
+    mcu_in, bit_out, ram_in
   );
 
   stimulus : process
   begin
     mcu_in <= mcu_in_initial;
+    mcu_in.a_oe <= enable;
+    ram_in <= ram_in_initial;
+
+    ram_in.ce <= enable;
+
+    write_ram(mcu_in, ram_in, "10100101", "1111000011110000");
+    write_ram(mcu_in, ram_in, "01011010", "0000111100001111");
+
+    read_ram(mcu_in, ram_in, bit_out, data, "1111000011110000");
 
-    write_ram(mcu_in, we, "10100101", "0000000000000001");
     wait;
   end process;
 
diff --git a/vhdl/mcu.vhd b/vhdl/mcu.vhd
index e20f4f6..7cf273b 100644
--- a/vhdl/mcu.vhd
+++ b/vhdl/mcu.vhd
@@ -4,8 +4,6 @@ use ieee.std_logic_1164.all;
 library ieee_proposed;
 use ieee_proposed.std_logic_1164_additions.all;
 
--- use work.mcu.all;
-
 package mcu is
 
   type mcu_in is record
@@ -23,6 +21,12 @@ package mcu is
     d_oe                : std_logic; 
   end record;
 
+  type ram_in is record
+    oe                  : std_logic;
+    ce                  : std_logic;
+    we                  : std_logic;
+  end record;
+
   procedure byte_out(
     signal mcu_in       : out mcu_in;
     byte                : in std_logic_vector(7 downto 0)
@@ -36,11 +40,19 @@ package mcu is
 
   procedure write_ram(
     signal mcu_in       : out mcu_in;
-    signal we           : out std_logic;
+    signal ram_in       : out ram_in;
     data                : in std_logic_vector(7 downto 0);
     address             : in std_logic_vector(15 downto 0)
   );
 
+  procedure read_ram(
+    signal mcu_in       : out mcu_in;
+    signal ram_in       : out ram_in;
+    signal bit_out      : in std_logic;
+    signal data         : inout std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)
+  );
+
   constant tClk         : time :=  100 ns;
   constant disable      : std_logic := '1';
   constant enable       : std_logic := '0';
@@ -53,6 +65,12 @@ package mcu is
     a_oe => '1',
     d_oe => '1'
   );
+  
+  constant ram_in_initial : ram_in := (
+    oe => '1',
+    ce => '1',
+    we => '1'
+  );
 
 end mcu;
 
@@ -95,11 +113,11 @@ package body mcu is
 
   procedure write_ram(
     signal mcu_in       : out mcu_in;
-    signal we           : out std_logic;
+    signal ram_in       : out ram_in;
     data                : in std_logic_vector(7 downto 0);
     address             : in std_logic_vector(15 downto 0)) is
   begin
-    report "write_ram: " & to_string(data);
+    report "write_ram: " & to_string(address) & "=" & to_string(data);
 
     -- TODO: busreq + wait for busack
     byte_out(mcu_in, data);
@@ -114,11 +132,39 @@ package body mcu is
     -- Enable A and D outputs
     mcu_in.a_oe <= enable;
     mcu_in.d_oe <= enable;
-    we <= enable;
+    ram_in.we <= enable;
+
+    wait for tClk;
+
+    ram_in.we <= disable;
+    mcu_in.d_oe <= disable;
+  end;
+
+  procedure read_ram(
+    signal mcu_in       : out mcu_in;
+    signal ram_in       : out ram_in;
+    signal bit_out      : in std_logic;
+    signal data         : inout std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)) is
+  begin
+    -- TODO: busreq + wait for busack
+    byte_out(mcu_in, "00000000");
+    byte_out(mcu_in, address(7 downto 0));
+    byte_out(mcu_in, address(15 downto 8));
 
+    mcu_in.byte_out_clk <= '0';
+    ram_in.oe <= enable;
     wait for tClk;
 
-    we <= disable;
+    -- Clock the data out on the A and D busses
+    mcu_in.byte_out_clk <= '1';
+    wait for tClk;
+
+    byte_in(mcu_in, bit_out, data);
+
+    ram_in.oe <= disable;
+
+    report "read_ram: " & to_string(address) & "=" & to_string(data);
   end;
 
 end mcu;
diff --git a/vhdl/mcu_interface.vhd b/vhdl/mcu_interface.vhd
index 86807a7..0aecbf2 100644
--- a/vhdl/mcu_interface.vhd
+++ b/vhdl/mcu_interface.vhd
@@ -13,8 +13,7 @@ entity mcu_interface is
     bit_out             : out std_logic;
     ah                  : out std_logic_vector(7 downto 0);
     al                  : out std_logic_vector(7 downto 0);
-    d_out               : out std_logic_vector(7 downto 0);
-    d_in                : in std_logic_vector(7 downto 0)
+    d                   : inout std_logic_vector(7 downto 0)
   );
 end;
 
@@ -63,14 +62,14 @@ begin
     sck => mcu_in.bit_clk,
     rck => mcu_in.byte_out_clk,
     gneg => mcu_in.d_oe,
-    qa => d_out(0),
-    qb => d_out(1),
-    qc => d_out(2),
-    qd => d_out(3),
-    qe => d_out(4),
-    qf => d_out(5),
-    qg => d_out(6),
-    qh => d_out(7),
+    qa => d(0),
+    qb => d(1),
+    qc => d(2),
+    qd => d(3),
+    qe => d(4),
+    qf => d(5),
+    qg => d(6),
+    qh => d(7),
     SCLRNeg => '1'
   );
 
@@ -81,13 +80,13 @@ begin
     clk => mcu_in.bit_clk,
     clkinh => '0',
     sh => mcu_in.byte_in_clk,
-    da => d_in(0),
-    db => d_in(1),
-    dc => d_in(2),
-    dd => d_in(3),
-    de => d_in(4),
-    df => d_in(5),
-    dg => d_in(6),
-    dh => d_in(7)
+    da => d(0),
+    db => d(1),
+    dc => d(2),
+    dd => d(3),
+    de => d(4),
+    df => d(5),
+    dg => d(6),
+    dh => d(7)
   );
 end;
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise
index 77f5b5a..53fce3b 100644
--- a/vhdl/ram-ice.xise
+++ b/vhdl/ram-ice.xise
@@ -128,7 +128,6 @@
 
   <libraries>
     <library xil_pn:name="fmf"/>
-    <library xil_pn:name="ieee"/>
     <library xil_pn:name="ieee_proposed"/>
   </libraries>