diff options
Diffstat (limited to 'hardware-v1')
| -rw-r--r-- | hardware-v1/.gitignore | 4 | ||||
| -rw-r--r-- | hardware-v1/eagle.epf | 352 | ||||
| -rw-r--r-- | hardware-v1/ram-ice.brd | 814 | ||||
| -rw-r--r-- | hardware-v1/ram-ice.sch | 1228 | ||||
| -rw-r--r-- | hardware-v1/untitled.pro | 25 |
5 files changed, 2423 insertions, 0 deletions
diff --git a/hardware-v1/.gitignore b/hardware-v1/.gitignore new file mode 100644 index 0000000..ba66ed2 --- /dev/null +++ b/hardware-v1/.gitignore @@ -0,0 +1,4 @@ +*.b#* +*.s#* +*.pro +eagle.epf diff --git a/hardware-v1/eagle.epf b/hardware-v1/eagle.epf new file mode 100644 index 0000000..ff48142 --- /dev/null +++ b/hardware-v1/eagle.epf @@ -0,0 +1,352 @@ +[Eagle] +Version="06 04 00" +Platform="Linux" +Serial="62191E841E-LSR-WLM-1EL" +Globals="Globals" +Desktop="Desktop" + +[Globals] +AutoSaveProject=1 +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/19inch.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/40xx.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/41xx.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/45xx.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ac-logic.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ttl-din.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-eu.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-de.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-us.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-us.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/751xx.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/advanced-test-technologies.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/agilent-technologies.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/allegro.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-II.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-III.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-stratix-iv.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/am29-memory.lbr" +UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/amd-mach.lbr" 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1200" +Window="Win_1" diff --git a/hardware-v1/ram-ice.brd b/hardware-v1/ram-ice.brd new file mode 100644 index 0000000..0d74c93 --- /dev/null +++ b/hardware-v1/ram-ice.brd @@ -0,0 +1,814 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.4"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.025" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/> +<layer number="20" name="Dimension" color="15" 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Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. +</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="0.6mm"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="999999"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" 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x1="21.0566" y1="40.005" x2="21.0566" y2="63.5" width="0" layer="19" extent="1-1"/> +</signal> +</signals> +</board> +</drawing> +</eagle> diff --git a/hardware-v1/ram-ice.sch b/hardware-v1/ram-ice.sch new file mode 100644 index 0000000..e06ad85 --- /dev/null +++ b/hardware-v1/ram-ice.sch @@ -0,0 +1,1228 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.4"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/> +<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/> +<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="no"/> +<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="no"/> +<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="no"/> +<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="no"/> +<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/> +<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/> +<layer number="31" name="tCream" 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active="yes"/> +<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/> +<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/> +<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/> +<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> +</layers> +<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R"> +<libraries> +<library name="74xx-eu"> +<description><b>TTL Devices, 74xx Series with European Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 +<li>http://icmaster.com/ViewCompare.asp +</ul> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="DIL16"> +<description><b>Dual In Line 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length="middle" direction="in"/> +<pin name="!CS" x="-12.7" y="-22.86" length="middle" direction="in"/> +<pin name="I/O1" x="12.7" y="22.86" length="middle" rot="R180"/> +<pin name="I/O2" x="12.7" y="20.32" length="middle" rot="R180"/> +<pin name="I/O3" x="12.7" y="17.78" length="middle" rot="R180"/> +<pin name="I/O4" x="12.7" y="15.24" length="middle" rot="R180"/> +<pin name="A11" x="-12.7" y="-5.08" length="middle" direction="in"/> +<pin name="A12" x="-12.7" y="-7.62" length="middle" direction="in"/> +<pin name="A13" x="-12.7" y="-10.16" length="middle" direction="in"/> +<pin name="A14" x="-12.7" y="-12.7" length="middle" direction="in"/> +</symbol> +<symbol name="VCCGND"> +<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text> +<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text> +<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text> +<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/> +<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="71256P" prefix="IC" uservalue="yes"> +<description><b>MEMORY</b></description> +<gates> +<gate name="G$1" symbol="71256" x="0" y="0"/> +<gate name="P" symbol="VCCGND" x="-25.4" y="0" addlevel="request"/> +</gates> +<devices> +<device name="" package="DIL28-6"> +<connects> +<connect gate="G$1" pin="!CS" pad="20"/> +<connect gate="G$1" pin="!OE" pad="22"/> +<connect gate="G$1" pin="!WE" pad="27"/> +<connect gate="G$1" pin="A0" pad="10"/> +<connect gate="G$1" pin="A1" pad="9"/> +<connect gate="G$1" pin="A10" pad="21"/> +<connect gate="G$1" pin="A11" pad="23"/> +<connect gate="G$1" pin="A12" pad="2"/> +<connect gate="G$1" pin="A13" pad="26"/> +<connect gate="G$1" pin="A14" pad="1"/> +<connect gate="G$1" pin="A2" pad="8"/> +<connect gate="G$1" pin="A3" pad="7"/> +<connect gate="G$1" pin="A4" pad="6"/> +<connect gate="G$1" pin="A5" pad="5"/> +<connect gate="G$1" pin="A6" pad="4"/> +<connect gate="G$1" pin="A7" pad="3"/> +<connect gate="G$1" pin="A8" pad="25"/> +<connect gate="G$1" pin="A9" pad="24"/> +<connect gate="G$1" pin="I/O1" pad="11"/> +<connect gate="G$1" pin="I/O2" pad="12"/> +<connect gate="G$1" pin="I/O3" pad="13"/> +<connect gate="G$1" pin="I/O4" pad="15"/> +<connect gate="G$1" pin="I/O5" pad="16"/> +<connect gate="G$1" pin="I/O6" pad="17"/> +<connect gate="G$1" pin="I/O7" pad="18"/> +<connect gate="G$1" pin="I/O8" pad="19"/> +<connect gate="P" pin="GND" pad="14"/> +<connect gate="P" pin="VCC" pad="28"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="" constant="no"/> +<attribute name="OC_FARNELL" value="unknown" constant="no"/> +<attribute name="OC_NEWARK" value="unknown" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="71256S" prefix="IC" uservalue="yes"> +<description><b>MEMORY</b></description> +<gates> +<gate name="G$1" symbol="71256" x="0" y="0"/> +<gate name="P" symbol="VCCGND" x="-22.86" y="2.54" addlevel="request"/> +</gates> +<devices> +<device name="" package="SO28-3"> +<connects> +<connect gate="G$1" pin="!CS" pad="20"/> +<connect gate="G$1" pin="!OE" pad="22"/> +<connect gate="G$1" pin="!WE" pad="27"/> +<connect gate="G$1" pin="A0" pad="10"/> +<connect gate="G$1" pin="A1" pad="9"/> +<connect gate="G$1" pin="A10" pad="21"/> +<connect gate="G$1" pin="A11" pad="23"/> +<connect gate="G$1" pin="A12" pad="2"/> +<connect gate="G$1" pin="A13" pad="26"/> +<connect gate="G$1" pin="A14" pad="1"/> +<connect gate="G$1" pin="A2" pad="8"/> +<connect gate="G$1" pin="A3" pad="7"/> +<connect gate="G$1" pin="A4" pad="6"/> +<connect gate="G$1" pin="A5" pad="5"/> +<connect gate="G$1" pin="A6" pad="4"/> +<connect gate="G$1" pin="A7" pad="3"/> +<connect gate="G$1" pin="A8" pad="25"/> +<connect gate="G$1" pin="A9" pad="24"/> +<connect gate="G$1" pin="I/O1" pad="11"/> +<connect gate="G$1" pin="I/O2" pad="12"/> +<connect gate="G$1" pin="I/O3" pad="13"/> +<connect gate="G$1" pin="I/O4" pad="15"/> +<connect gate="G$1" pin="I/O5" pad="16"/> +<connect gate="G$1" pin="I/O6" pad="17"/> +<connect gate="G$1" pin="I/O7" pad="18"/> +<connect gate="G$1" pin="I/O8" pad="19"/> +<connect gate="P" pin="GND" pad="14"/> +<connect gate="P" pin="VCC" pad="28"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="IDT71256SA20YG" constant="no"/> +<attribute name="OC_FARNELL" value="1218010" constant="no"/> +<attribute name="OC_NEWARK" value="34M6449" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="supply1"> +<description><b>Supply Symbols</b><p> + GND, VCC, 0V, +5V, -5V, etc.<p> + Please keep in mind, that these devices are necessary for the + automatic wiring of the supply signals.<p> + The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> + In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> + <author>Created by librarian@cadsoft.de</author></description> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="IC1" library="74xx-eu" deviceset="74*165" device="D" technology="AC"/> +<part name="IC2" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC3" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC4" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC5" library="memory-idt" deviceset="71256S" device=""/> +<part name="P+1" library="supply1" deviceset="VCC" device=""/> +<part name="IC6" library="memory-idt" deviceset="71256P" device=""/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="IC1" gate="A" x="162.56" y="83.82"/> +<instance part="IC2" gate="A" x="162.56" y="40.64" rot="R180"/> +<instance part="IC3" gate="A" x="45.72" y="88.9"/> +<instance part="IC4" gate="A" x="45.72" y="45.72"/> +<instance part="IC5" gate="G$1" x="101.6" y="55.88"/> +<instance part="P+1" gate="VCC" x="27.94" y="109.22"/> +<instance part="IC6" gate="G$1" x="233.68" y="58.42"/> +</instances> +<busses> +<bus name="A[0..7]"> +<segment> +<wire x1="63.5" y1="99.06" x2="63.5" y2="81.28" width="0.762" layer="92"/> +<wire x1="63.5" y1="81.28" x2="81.28" y2="81.28" width="0.762" layer="92"/> +<wire x1="81.28" y1="81.28" x2="81.28" y2="60.96" width="0.762" layer="92"/> +</segment> +</bus> +<bus name="A[8..14]"> +<segment> +<wire x1="81.28" y1="58.42" x2="81.28" y2="35.56" width="0.762" layer="92"/> +<wire x1="81.28" y1="35.56" x2="63.5" y2="35.56" width="0.762" layer="92"/> +<wire x1="63.5" y1="35.56" x2="63.5" y2="55.88" width="0.762" layer="92"/> +</segment> +</bus> +<bus name="D[0..7]"> +<segment> +<wire x1="134.62" y1="96.52" x2="134.62" y2="78.74" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="134.62" y2="30.48" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="121.92" y2="78.74" width="0.762" layer="92"/> +<wire x1="121.92" y1="78.74" x2="121.92" y2="60.96" width="0.762" layer="92"/> +</segment> +</bus> +</busses> +<nets> +<net name="A1" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QB"/> +<wire x1="58.42" y1="96.52" x2="63.5" y2="96.52" width="0.1524" layer="91"/> +<label x="58.42" y="96.52" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A1"/> +<wire x1="81.28" y1="76.2" x2="88.9" y2="76.2" width="0.1524" layer="91"/> +<label x="88.9" y="76.2" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A0" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QA"/> +<wire x1="58.42" y1="99.06" x2="63.5" y2="99.06" width="0.1524" layer="91"/> +<label x="58.42" y="99.06" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A0"/> +<wire x1="81.28" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/> +<label x="88.9" y="78.74" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A3" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QD"/> +<wire x1="63.5" y1="91.44" x2="58.42" y2="91.44" width="0.1524" layer="91"/> +<label x="58.42" y="91.44" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A3"/> +<wire x1="81.28" y1="71.12" x2="88.9" y2="71.12" width="0.1524" layer="91"/> +<label x="88.9" y="71.12" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A2" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QC"/> +<wire x1="63.5" y1="93.98" x2="58.42" y2="93.98" width="0.1524" layer="91"/> +<label x="58.42" y="93.98" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A2"/> +<wire x1="81.28" y1="73.66" x2="88.9" y2="73.66" width="0.1524" layer="91"/> +<label x="88.9" y="73.66" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A4" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QE"/> +<wire x1="63.5" y1="88.9" x2="58.42" y2="88.9" width="0.1524" layer="91"/> +<label x="58.42" y="88.9" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A4"/> +<wire x1="88.9" y1="68.58" x2="81.28" y2="68.58" width="0.1524" layer="91"/> +<label x="88.9" y="68.58" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A5" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QF"/> +<wire x1="63.5" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/> +<label x="58.42" y="86.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A5"/> +<wire x1="88.9" y1="66.04" x2="81.28" y2="66.04" width="0.1524" layer="91"/> +<label x="88.9" y="66.04" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A6" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QG"/> +<wire x1="63.5" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/> +<label x="58.42" y="83.82" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A6"/> +<wire x1="88.9" y1="63.5" x2="81.28" y2="63.5" width="0.1524" layer="91"/> +<label x="88.9" y="63.5" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A7" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QH"/> +<wire x1="63.5" y1="81.28" x2="58.42" y2="81.28" width="0.1524" layer="91"/> +<label x="58.42" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A7"/> +<wire x1="88.9" y1="60.96" x2="81.28" y2="60.96" width="0.1524" layer="91"/> +<label x="88.9" y="60.96" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A8" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QA"/> +<wire x1="58.42" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/> +<label x="58.42" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A8"/> +<wire x1="88.9" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/> +<label x="88.9" y="58.42" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A9" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QB"/> +<wire x1="58.42" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/> +<label x="58.42" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A9"/> +<wire x1="88.9" y1="55.88" x2="81.28" y2="55.88" width="0.1524" layer="91"/> +<label x="88.9" y="55.88" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A10" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QC"/> +<wire x1="58.42" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/> +<label x="58.42" y="50.8" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A10"/> +<wire x1="88.9" y1="53.34" x2="81.28" y2="53.34" width="0.1524" layer="91"/> +<label x="88.9" y="53.34" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A11" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QD"/> +<wire x1="58.42" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/> +<label x="58.42" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A11"/> +<wire x1="88.9" y1="50.8" x2="81.28" y2="50.8" width="0.1524" layer="91"/> +<label x="88.9" y="50.8" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A12" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QE"/> +<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/> +<label x="58.42" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A12"/> +<wire x1="88.9" y1="48.26" x2="81.28" y2="48.26" width="0.1524" layer="91"/> +<label x="88.9" y="48.26" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A13" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QF"/> +<wire x1="58.42" y1="43.18" x2="63.5" y2="43.18" width="0.1524" layer="91"/> +<label x="58.42" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A13"/> +<wire x1="81.28" y1="45.72" x2="88.9" y2="45.72" width="0.1524" layer="91"/> +<label x="88.9" y="45.72" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="A14" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QG"/> +<wire x1="58.42" y1="40.64" x2="63.5" y2="40.64" width="0.1524" layer="91"/> +<label x="58.42" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A14"/> +<wire x1="88.9" y1="43.18" x2="81.28" y2="43.18" width="0.1524" layer="91"/> +<label x="88.9" y="43.18" size="1.778" layer="95" rot="MR0"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QH*"/> +<wire x1="58.42" y1="76.2" x2="58.42" y2="66.04" width="0.1524" layer="91"/> +<wire x1="58.42" y1="66.04" x2="30.48" y2="66.04" width="0.1524" layer="91"/> +<wire x1="30.48" y1="66.04" x2="30.48" y2="55.88" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="SER"/> +<wire x1="30.48" y1="55.88" x2="33.02" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A_EN" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="G"/> +<wire x1="33.02" y1="76.2" x2="22.86" y2="76.2" width="0.1524" layer="91"/> +<wire x1="22.86" y1="76.2" x2="22.86" y2="33.02" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="G"/> +<wire x1="22.86" y1="33.02" x2="22.86" y2="25.4" width="0.1524" layer="91"/> +<wire x1="33.02" y1="33.02" x2="22.86" y2="33.02" width="0.1524" layer="91"/> +<wire x1="22.86" y1="25.4" x2="5.08" y2="25.4" width="0.1524" layer="91"/> +<label x="5.08" y="27.94" size="1.778" layer="95"/> +<junction x="22.86" y="33.02"/> +</segment> +</net> +<net name="D0" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="A"/> +<wire x1="134.62" y1="96.52" x2="149.86" y2="96.52" width="0.1524" layer="91"/> +<label x="137.16" y="96.52" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QA"/> +<wire x1="134.62" y1="30.48" x2="149.86" y2="30.48" width="0.1524" layer="91"/> +<label x="137.16" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O1"/> +<wire x1="114.3" y1="78.74" x2="121.92" y2="78.74" width="0.1524" layer="91"/> +<label x="116.84" y="78.74" size="1.778" layer="95"/> +</segment> +</net> +<net name="D1" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="B"/> +<wire x1="134.62" y1="93.98" x2="149.86" y2="93.98" width="0.1524" layer="91"/> +<label x="137.16" y="93.98" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QB"/> +<wire x1="134.62" y1="33.02" x2="149.86" y2="33.02" width="0.1524" layer="91"/> +<label x="137.16" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O2"/> +<wire x1="114.3" y1="76.2" x2="121.92" y2="76.2" width="0.1524" layer="91"/> +<label x="116.84" y="76.2" size="1.778" layer="95"/> +</segment> +</net> +<net name="D2" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="C"/> +<wire x1="134.62" y1="91.44" x2="149.86" y2="91.44" width="0.1524" layer="91"/> +<label x="137.16" y="91.44" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QC"/> +<wire x1="134.62" y1="35.56" x2="149.86" y2="35.56" width="0.1524" layer="91"/> +<label x="137.16" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O3"/> +<wire x1="114.3" y1="73.66" x2="121.92" y2="73.66" width="0.1524" layer="91"/> +<label x="116.84" y="73.66" size="1.778" layer="95"/> +</segment> +</net> +<net name="D3" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="D"/> +<wire x1="134.62" y1="88.9" x2="149.86" y2="88.9" width="0.1524" layer="91"/> +<label x="137.16" y="88.9" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QD"/> +<wire x1="134.62" y1="38.1" x2="149.86" y2="38.1" width="0.1524" layer="91"/> +<label x="137.16" y="38.1" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O4"/> +<wire x1="121.92" y1="71.12" x2="114.3" y2="71.12" width="0.1524" layer="91"/> +<label x="116.84" y="71.12" size="1.778" layer="95"/> +</segment> +</net> +<net name="D4" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="E"/> +<wire x1="134.62" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/> +<label x="137.16" y="86.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QE"/> +<wire x1="134.62" y1="40.64" x2="149.86" y2="40.64" width="0.1524" layer="91"/> +<label x="137.16" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O5"/> +<wire x1="121.92" y1="68.58" x2="114.3" y2="68.58" width="0.1524" layer="91"/> +<label x="116.84" y="68.58" size="1.778" layer="95"/> +</segment> +</net> +<net name="D5" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="F"/> +<wire x1="134.62" y1="83.82" x2="149.86" y2="83.82" width="0.1524" layer="91"/> +<label x="137.16" y="83.82" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QF"/> +<wire x1="134.62" y1="43.18" x2="149.86" y2="43.18" width="0.1524" layer="91"/> +<label x="137.16" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O6"/> +<wire x1="114.3" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/> +<label x="116.84" y="66.04" size="1.778" layer="95"/> +</segment> +</net> +<net name="D6" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="G"/> +<wire x1="134.62" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/> +<label x="137.16" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QG"/> +<wire x1="134.62" y1="45.72" x2="149.86" y2="45.72" width="0.1524" layer="91"/> +<label x="137.16" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O7"/> +<wire x1="114.3" y1="63.5" x2="121.92" y2="63.5" width="0.1524" layer="91"/> +<label x="116.84" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="D7" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="H"/> +<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.1524" layer="91"/> +<label x="137.16" y="78.74" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QH"/> +<wire x1="134.62" y1="48.26" x2="149.86" y2="48.26" width="0.1524" layer="91"/> +<label x="137.16" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O8"/> +<wire x1="114.3" y1="60.96" x2="121.92" y2="60.96" width="0.1524" layer="91"/> +<label x="116.84" y="60.96" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QH*"/> +<wire x1="58.42" y1="33.02" x2="60.96" y2="33.02" width="0.1524" layer="91"/> +<wire x1="60.96" y1="33.02" x2="60.96" y2="15.24" width="0.1524" layer="91"/> +<wire x1="60.96" y1="15.24" x2="180.34" y2="15.24" width="0.1524" layer="91"/> +<wire x1="180.34" y1="15.24" x2="180.34" y2="30.48" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="SER"/> +<wire x1="180.34" y1="30.48" x2="175.26" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="QH*"/> +<wire x1="149.86" y1="53.34" x2="142.24" y2="53.34" width="0.1524" layer="91"/> +<wire x1="142.24" y1="53.34" x2="142.24" y2="99.06" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="SER"/> +<wire x1="142.24" y1="99.06" x2="149.86" y2="99.06" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D_IN" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="SER"/> +<wire x1="33.02" y1="99.06" x2="20.32" y2="99.06" width="0.1524" layer="91"/> +<wire x1="20.32" y1="99.06" x2="20.32" y2="33.02" width="0.1524" layer="91"/> +<wire x1="20.32" y1="33.02" x2="5.08" y2="33.02" width="0.1524" layer="91"/> +<label x="5.08" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="D_CLK" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="SCK"/> +<wire x1="33.02" y1="93.98" x2="17.78" y2="93.98" width="0.1524" layer="91"/> +<wire x1="17.78" y1="93.98" x2="17.78" y2="50.8" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="SCK"/> +<wire x1="17.78" y1="50.8" x2="33.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="17.78" y1="50.8" x2="17.78" y2="40.64" width="0.1524" layer="91"/> +<wire x1="17.78" y1="40.64" x2="5.08" y2="40.64" width="0.1524" layer="91"/> +<label x="5.08" y="43.18" size="1.778" layer="95"/> +<wire x1="17.78" y1="40.64" x2="17.78" y2="7.62" width="0.1524" layer="91"/> +<wire x1="17.78" y1="7.62" x2="187.96" y2="7.62" width="0.1524" layer="91"/> +<wire x1="187.96" y1="7.62" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="SCK"/> +<wire x1="175.26" y1="35.56" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<wire x1="187.96" y1="35.56" x2="187.96" y2="60.96" width="0.1524" layer="91"/> +<wire x1="187.96" y1="60.96" x2="144.78" y2="60.96" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="CLK"/> +<wire x1="149.86" y1="73.66" x2="144.78" y2="73.66" width="0.1524" layer="91"/> +<wire x1="144.78" y1="73.66" x2="144.78" y2="60.96" width="0.1524" layer="91"/> +<junction x="17.78" y="40.64"/> +<junction x="187.96" y="35.56"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="RCK"/> +<wire x1="175.26" y1="43.18" x2="185.42" y2="43.18" width="0.1524" layer="91"/> +<wire x1="185.42" y1="43.18" x2="185.42" y2="10.16" width="0.1524" layer="91"/> +<wire x1="185.42" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<wire x1="25.4" y1="10.16" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="RCK"/> +<wire x1="33.02" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="RCK"/> +<wire x1="33.02" y1="86.36" x2="25.4" y2="86.36" width="0.1524" layer="91"/> +<wire x1="25.4" y1="86.36" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="SH/!LD"/> +<wire x1="149.86" y1="68.58" x2="147.32" y2="68.58" width="0.1524" layer="91"/> +<wire x1="147.32" y1="68.58" x2="147.32" y2="63.5" width="0.1524" layer="91"/> +<wire x1="147.32" y1="63.5" x2="185.42" y2="63.5" width="0.1524" layer="91"/> +<wire x1="185.42" y1="63.5" x2="185.42" y2="43.18" width="0.1524" layer="91"/> +<junction x="25.4" y="43.18"/> +<junction x="185.42" y="43.18"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="SCL"/> +<wire x1="33.02" y1="48.26" x2="27.94" y2="48.26" width="0.1524" layer="91"/> +<wire x1="27.94" y1="48.26" x2="27.94" y2="91.44" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="SCL"/> +<wire x1="27.94" y1="91.44" x2="27.94" y2="106.68" width="0.1524" layer="91"/> +<wire x1="33.02" y1="91.44" x2="27.94" y2="91.44" width="0.1524" layer="91"/> +<junction x="27.94" y="91.44"/> +<pinref part="P+1" gate="VCC" pin="VCC"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/hardware-v1/untitled.pro b/hardware-v1/untitled.pro new file mode 100644 index 0000000..d77689b --- /dev/null +++ b/hardware-v1/untitled.pro @@ -0,0 +1,25 @@ +EAGLE AutoRouter Statistics: + +Job : /home/trygvis/dev/io.trygvis/2013/02/ram-ice/untitled.brd + +Start at : 01:56:21 (2/10/13) +End at : 01:56:21 (2/10/13) +Elapsed time : 00:00:00 + +Signals : 30 RoutingGrid: 50 mil Layers: 2 +Connections : 43 predefined: 0 ( 0 Vias ) + +Router memory : 24708 + +Passname : Busses Route Optimize1 Optimize2 Optimize3 Optimize4 + +Time per pass : 00:00:00 00:00:00 00:00:00 00:00:00 00:00:00 00:00:00 +Number of Ripups : 0 0 0 0 0 0 +max. Level : 0 0 0 0 0 0 +max. Total : 0 0 0 0 0 0 + +Routed : 0 0 0 0 0 0 +Vias : 0 0 0 0 0 0 +Resolution : 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % + +Final : 0.0% finished |