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Diffstat (limited to 'vhdl/TEST_AS7C256A.vhd')
| -rw-r--r-- | vhdl/TEST_AS7C256A.vhd | 264 |
1 files changed, 264 insertions, 0 deletions
diff --git a/vhdl/TEST_AS7C256A.vhd b/vhdl/TEST_AS7C256A.vhd new file mode 100644 index 0000000..5f49d4e --- /dev/null +++ b/vhdl/TEST_AS7C256A.vhd @@ -0,0 +1,264 @@ +-- Testbench for Alliance Semiconductors ASync SRAM + +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE testbench_arch OF testbench IS + -- Clock + CONSTANT tCYC : TIME := 12 ns; + CONSTANT tWC : TIME := 10 ns; + CONSTANT tRC : TIME := 10 ns; + CONSTANT t1 : TIME := 1 ns; + CONSTANT twz : TIME := 5 ns; + CONSTANT tcw : TIME := 7 ns; + -- Bus Width and Data Bus + CONSTANT addr_bits : INTEGER := 15; + CONSTANT data_bits : INTEGER := 8; + + COMPONENT AS7C256A + PORT ( + Address : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + DataIO : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + OE_bar : IN STD_LOGIC; + CE_bar : IN STD_LOGIC; + WE_bar : IN STD_LOGIC + ); + END COMPONENT; + + FOR ALL: AS7C256A USE ENTITY WORK.AS7C256A (behave); + + SIGNAL Address : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + SIGNAL DataIO : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL OE_bar : STD_LOGIC; + SIGNAL CE_bar : STD_LOGIC; + SIGNAL WE_bar : STD_LOGIC; + + SIGNAL Done : BOOLEAN := FALSE; + + BEGIN + U1 : AS7C256A PORT MAP (Address, DataIO, OE_bar, CE_bar, WE_bar); + + Stimulus : PROCESS + -- Deselect + PROCEDURE deselect IS + BEGIN + OE_bar <= '1'; + CE_bar <= '1'; + WE_bar <= '1'; + Address <= (OTHERS => '0'); + DataIO <= (OTHERS => 'Z'); + + WAIT FOR tCYC; + END; + + PROCEDURE write_ce (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR (tCYC-twz); + + CE_bar <= '1'; + WAIT FOR t1; + + END; + + PROCEDURE write_we (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR tCYC; + + WE_bar <= '1'; + WAIT FOR t1; + + END; + + + PROCEDURE write_wece (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR tCYC; + + WE_bar <= '1'; + CE_bar <= '1'; + WAIT FOR t1; + + END; + + PROCEDURE write_add (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + DataIO <= data_in; + WAIT FOR tWC; + + + END; + + PROCEDURE write_data (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR (tWC/2); + + + END; + + + + PROCEDURE read_ce (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '0'; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR tCYC; + + END; + + PROCEDURE read_add (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '0'; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR tRC; + + END; + + + PROCEDURE read_oe (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR (7*t1); + OE_bar <= '0'; + WAIT FOR tCYC; + + END; + + + + + + + + + BEGIN + -- Test vectors + deselect; + --deselect; + + --WWRR (we/ce controlled) + write_ce("000000000000001", + "00000001"); + + write_we("000000000000010", + "00000010"); + + read_ce ("000000000000001"); + + + read_ce ("000000000000010"); + deselect; + --WWRR ( only address controlled) + write_add("000000000000011", + "00000011"); + + write_add("000000000000100", + "00000100"); + + read_add ("000000000000011"); + + + read_add ("000000000000100"); + deselect; + + --WRWR (oe read controlled) + write_wece("000000000000101", + "00000101"); + + read_oe ("000000000000101"); + + + write_we("000000000000110", + "00000110"); + + read_oe ("000000000000110"); + + deselect; + --WRWR ( Data change) + write_add("000000000000111", + "00000001"); + + write_add("000000000000111", + "00000111"); + + read_ce ("000000000000111"); + + + write_data("000000000001000", + "00000011"); + + write_add("000000000001000", + "00001000"); + + read_ce ("000000000001000"); + + + + deselect; + + + + Done <= TRUE; + + + assert false report "end of test" severity note; + + WAIT; + END PROCESS; + + + END testbench_arch; + |