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+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.mcu.all;
+
+entity ice is
+ port (
+ mcu_in : in mcu_in;
+ bit_out : out std_logic;
+ oe : in std_logic;
+ ce : in std_logic;
+ we : in std_logic
+ );
+end ice;
+
+architecture behaviour of ice is
+ signal ah : std_logic_vector(15 downto 8);
+ signal al : std_logic_vector(7 downto 0);
+ signal d : std_logic_vector(7 downto 0);
+
+ signal ram_address : std_logic_vector(14 downto 0);
+begin
+ mcu_interface : entity work.mcu_interface(behaviour) port map(
+ mcu_in,
+ bit_out,
+ ah,
+ al,
+ d, -- d_out,
+ d -- d_in
+ );
+
+ address : ram_address <= ah(14 downto 8) & al;
+
+ ram : entity work.as7c256a port map(
+ address => ram_address,
+ dataio => d,
+ oe_bar => oe,
+ ce_bar => ce,
+ we_bar => we
+ );
+
+end;