diff options
Diffstat (limited to 'vhdl/ram-ice.xise')
| -rw-r--r-- | vhdl/ram-ice.xise | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise new file mode 100644 index 0000000..a5bd50b --- /dev/null +++ b/vhdl/ram-ice.xise @@ -0,0 +1,134 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="fmf/conversions.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/ecl_package.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/ecl_utils.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/ff_package.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/gen_utils.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/memory.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/state_tab_package.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/std165.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="fmf/std595.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <library xil_pn:name="fmf"/> + </file> + <file xil_pn:name="mcu_interface_tb.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="37"/> + </file> + <file xil_pn:name="mcu_interface.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="ieee_proposed/std_logic_1164_additions.vhdl" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="66"/> + <library xil_pn:name="ieee_proposed"/> + </file> + </files> + + <properties> + <property xil_pn:name="Device" xil_pn:value="xc95*xl" xil_pn:valueState="default"/> + <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mcu_interface|behaviour" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="mcu_interface.vhd" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mcu_interface" xil_pn:valueState="non-default"/> + <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="*" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mcu_interface_tb" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mcu_interface_tb" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-*" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mcu_interface_tb|behaviour" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="ram-ice" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-10T14:06:24" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CC41C5D21C862F16AE667C80E5797D8C" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries> + <library xil_pn:name="fmf"/> + <library xil_pn:name="ieee"/> + <library xil_pn:name="ieee_proposed"/> + </libraries> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> |