diff options
Diffstat (limited to 'vhdl/ram-ice.xise')
| -rw-r--r-- | vhdl/ram-ice.xise | 54 |
1 files changed, 32 insertions, 22 deletions
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise index a5bd50b..77f5b5a 100644 --- a/vhdl/ram-ice.xise +++ b/vhdl/ram-ice.xise @@ -15,14 +15,6 @@ <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> <files> - <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> - <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/> - </file> - <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> <file xil_pn:name="fmf/conversions.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> @@ -39,12 +31,12 @@ <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/ff_package.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/gen_utils.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="fmf"/> </file> @@ -59,53 +51,71 @@ <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/std165.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/std595.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="mcu_interface_tb.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="37"/> </file> <file xil_pn:name="mcu_interface.vhd" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="ieee_proposed/std_logic_1164_additions.vhdl" xil_pn:type="FILE_VHDL"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="66"/> <library xil_pn:name="ieee_proposed"/> </file> + <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="57"/> + </file> + <file xil_pn:name="AS7C256A.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="59"/> + </file> + <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="66"/> + </file> + <file xil_pn:name="mcu.vhd" xil_pn:type="FILE_VHDL"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="67"/> + </file> </files> <properties> + <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="ice_tb.wcfg" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc95*xl" xil_pn:valueState="default"/> <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mcu_interface|behaviour" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top File" xil_pn:value="mcu_interface.vhd" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mcu_interface" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ice|behaviour" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="ice.vhd" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ice" xil_pn:valueState="non-default"/> <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/> <property xil_pn:name="Package" xil_pn:value="*" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> - <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mcu_interface_tb" xil_pn:valueState="non-default"/> - <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mcu_interface_tb" xil_pn:valueState="non-default"/> - <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ice_tb" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ice_tb" xil_pn:valueState="non-default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="20us" xil_pn:valueState="non-default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-*" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> - <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mcu_interface_tb|behaviour" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ice_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="ram-ice" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-10T14:06:24" xil_pn:valueState="non-default"/> |