diff options
Diffstat (limited to 'vhdl')
| -rw-r--r-- | vhdl/ram-ice.xise | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise index 53fce3b..337c9a3 100644 --- a/vhdl/ram-ice.xise +++ b/vhdl/ram-ice.xise @@ -32,12 +32,12 @@ </file> <file xil_pn:name="fmf/ff_package.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/gen_utils.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/memory.vhd" xil_pn:type="FILE_VHDL"> @@ -47,17 +47,17 @@ </file> <file xil_pn:name="fmf/state_tab_package.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/std165.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="fmf/std595.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> <library xil_pn:name="fmf"/> </file> <file xil_pn:name="mcu_interface_tb.vhd" xil_pn:type="FILE_VHDL"> @@ -66,16 +66,16 @@ </file> <file xil_pn:name="mcu_interface.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> <file xil_pn:name="ieee_proposed/std_logic_1164_additions.vhdl" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="66"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> <library xil_pn:name="ieee_proposed"/> </file> <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> - <association xil_pn:name="Implementation" xil_pn:seqID="57"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="AS7C256A.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |