correct linking, putting the assembly code in .text with proper linking script made ld recognise the functions as thumb instructions.

6 files changed, 75 insertions, 35 deletions

diff --git a/README.md b/README.md
index 4661972..5a3315d 100644
--- a/README.md
+++ b/README.md
@@ -4,6 +4,10 @@
 * http://embedded.kleier.selfhost.me/lockup.php
 * http://fun-tech.se/stm32/linker/index.php
 * Developing a Generic Hard Fault handler for ARM Cortex-M3/Cortex-M4: https://community.arm.com/servlet/JiveServlet/previewBody/7835-102-2-12371/Developing%20a%20Generic%20Hard%20Fault%20handler%20for%20ARM.pdf
+* Schematic: http://img.banggood.com/file/products/20150205235330SKU120191.pdf
+* http://www.st.com/web/en/resource/technical/document/datasheet/CD00161566.pdf
+* http://www.banggood.com/ARM-Cortex-M3-STM32F103C8T6-STM32-Minimum-System-Development-Board-p-920184.html
+* http://www.lctech-inc.com/Hardware/Detail.aspx?id=0172e854-77b0-43d5-b300-68e570c914fd
 
         
 * http://www.st.com/web/en/catalog/tools/PF257890
@@ -11,11 +15,11 @@
         
 # Programming with OpenOCD
         
-        reset halt
-        flash probe 0 
-        stm32f1x mass_erase 0
-        flash write_bank 0 test1.elf.bin 0
-        reset run 
+    reset halt
+    flash probe 0 
+    stm32f1x mass_erase 0
+    flash write_bank 0 test1.elf.bin 0
+    reset run 
 
 # Registers
 
@@ -47,7 +51,45 @@ This error is always handled by the hard fault handler.
 When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception.
 [0]	-	Reserved.
 
+### Faults
+
+    HFSR = 0x40000000 => FORCED, double error, check the other flags
+
 ## Debug Fault Status Register: 0xE000ED30
 
+## Configurable Fault Status Register: 0xE000ED28
+
+The following subsections describe the subregisters that make up the CFSR:
+* MemManage Fault Status Register
+* BusFault Status Register
+* UsageFault Status Register.
+
+    CFSR = 0x00020000 => INVSTATE (Invalid state)
+
+* [1] INVSTATE	Invalid state UsageFault:
+    * 0 = no invalid state UsageFault
+    * 1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR.
+    * When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR.
+    * This bit is not set to 1 if an undefined instruction uses the EPSR.
 
 ## Auxiliary Fault Status Register: 0xE000ED3C
+
+# GDB Tips
+
+## Stack straces
+
+Show stack trace:
+
+    (gdb) bt
+    #0  0x08000050 in HardFault_Handler ()
+    #1  <signal handler called>
+    #2  0x08000044 in _Reset_Handler ()
+
+Show details on each frame:
+
+    (gdb) info frame 0
+    Stack frame at 0x20000fe0:
+     pc = 0x8000050 in HardFault_Handler; saved pc = 0xfffffff9
+     called by frame at 0x20001000
+     Arglist at 0x20000fe0, args: 
+     Locals at 0x20000fe0, Previous frame's sp is 0x20000fe0
diff --git a/cmake/stm32.ld b/cmake/stm32.ld
index 48e3d0c..ea06a98 100644
--- a/cmake/stm32.ld
+++ b/cmake/stm32.ld
@@ -24,13 +24,14 @@ SECTIONS
 {
     .text :
     {
-        KEEP(*(isr_vectors))
-        *(.text.main)
+        *(.isr_vectors)
+        init.s:(.text)
+        *(.text)
         KEEP(*(.text.*))
-        /*
-        *(.text.*)
-        KEEP(*(.text.high))
-        KEEP(*(.text.low))
-        /**/
     } >FLASH
+
+    .data :
+    {
+        *(.data*)
+    } >RAM
 }
diff --git a/gdb-start b/gdb-start
index 5fda96f..e46fd1c 100644
--- a/gdb-start
+++ b/gdb-start
@@ -16,14 +16,14 @@ monitor stm32f1x.cpu mwb 0x20000000 0x5a 0x5000
 
 define flash_test1
 file build/test1.elf
-load build/test1.elf
+#load build/test1.elf
 monitor reset halt
 monitor flash probe 0
 monitor stm32f1x mass_erase 0
-monitor flash write_bank 0 test1.elf.bin 0
 monitor stm32f1x.cpu mwb 0x20000000 0x5a 20480
+monitor flash write_bank 0 test1.elf.bin
+delete breakpoint
+hbreak main
 end
 
 monitor reset halt
-#hbreak main
-jump main
diff --git a/init.s b/init.s
index 5897202..122a6ad 100644
--- a/init.s
+++ b/init.s
@@ -1,12 +1,14 @@
-; https://github.com/dwelch67/stm32_samples
-; http://stackoverflow.com/questions/9565921/cortex-m3-initialisation
+/*
+https://github.com/dwelch67/stm32_samples
+http://stackoverflow.com/questions/9565921/cortex-m3-initialisation
+*/
 
 .syntax unified
 .cpu cortex-m3
 .thumb
 
-.section isr_vectors
-.thumb_func
+.section .isr_vectors
+
 .global vectors
 vectors:
 stacktop: .word 0x20001000
@@ -26,9 +28,8 @@ stacktop: .word 0x20001000
 .word hang2
 .word hang2
 
-.global fault_code
-fault_code:
-.word 0
+/* VERY significant */
+.section .text
 
 .thumb_func
 .global _Reset_Handler
@@ -42,7 +43,6 @@ hang2:
 
 .thumb_func
 NMI_Handler:
-    movs r0, #1
     b hang2
 
 .thumb_func
@@ -55,15 +55,14 @@ HardFault_Handler:
 
 .thumb_func
 MemManage_Handler:
-    movs r0, #3
     b hang2
 
 .thumb_func
 BusFault_Handler:
-    movs r0, #4
     b hang2
 
 .thumb_func
 UsageFault_Handler:
-    mov r0, #5
     b hang2
+
+.end
diff --git a/openocd.cfg b/openocd.cfg
index ba3b349..05e7ef2 100644
--- a/openocd.cfg
+++ b/openocd.cfg
@@ -1,12 +1,8 @@
 # openocd
 # Chip: STM32F103C8T6, 8=64k flash
-# Schematic: http://img.banggood.com/file/products/20150205235330SKU120191.pdf
-# http://www.st.com/web/en/resource/technical/document/datasheet/CD00161566.pdf
-# http://www.banggood.com/ARM-Cortex-M3-STM32F103C8T6-STM32-Minimum-System-Development-Board-p-920184.html
-# http://www.lctech-inc.com/Hardware/Detail.aspx?id=0172e854-77b0-43d5-b300-68e570c914fd
 
 # Work-area size (RAM size) = 20kB for STM32F103Tx/STM32F103Cx/STM32F103Rx/STM32F103Vx devices
-set WORKAREASIZE 0x5000
+set WORKAREASIZE 0x1000
 
 #interface ftdi
 #ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
diff --git a/test1.cpp b/test1.cpp
index 0e6ffe6..85dee38 100644
--- a/test1.cpp
+++ b/test1.cpp
@@ -18,6 +18,7 @@ extern "C" void high();
 extern "C" void low();
 
 SCB_Type *__SCB = ((SCB_Type *) SCB_BASE);
+//extern SCB_Type *__SCB;
 
 struct hardfault_data_t {
     uint32_t r0;
@@ -54,10 +55,11 @@ void HardFault_Handler_C(uint32_t * hardfault_args) {
  */
 
 int main() {
-//    SystemInit();
+    SystemInit();
+    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTPENDED_Msk | SCB_SHCSR_BUSFAULTENA_Msk;
 
-//    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-//    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA, ENABLE);
 
 //    GPIO_InitTypeDef init;
 //    GPIO_StructInit(&init);