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| author | Trygve Laugstøl <trygvis@inamo.no> | 2017-01-25 22:23:13 +0100 |
|---|---|---|
| committer | Trygve Laugstøl <trygvis@inamo.no> | 2017-01-25 22:23:17 +0100 |
| commit | 2fff65aed2477a503c72629d27e2a330d30c02d1 (patch) | |
| tree | 96fd9f2f8151e266c0cf8563a714d7bab8aa7cb0 /tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver | |
| parent | 41fdd2b1f35bcb4224fdb8fee2b959e09d1f5916 (diff) | |
| download | stm32f103-playground-2fff65aed2477a503c72629d27e2a330d30c02d1.tar.gz stm32f103-playground-2fff65aed2477a503c72629d27e2a330d30c02d1.tar.bz2 stm32f103-playground-2fff65aed2477a503c72629d27e2a330d30c02d1.tar.xz stm32f103-playground-2fff65aed2477a503c72629d27e2a330d30c02d1.zip | |
o Seemingly working Mutexes.
o Dropping the privileged/unprivileged split for now.
Diffstat (limited to 'tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver')
16 files changed, 0 insertions, 6748 deletions
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h deleted file mode 100644 index c465d33..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h deleted file mode 100644 index 275c5e1..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h deleted file mode 100644 index 7ce6896..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CEC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CEC_H -#define __STM32F10x_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - - -/** @defgroup CEC_Exported_Types - * @{ - */ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. - This parameter can be a value of @ref CEC_BitTiming_Mode */ - uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. - This parameter can be a value of @ref CEC_BitPeriod_Mode */ -}CEC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_BitTiming_Mode - * @{ - */ -#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ -#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ - -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ - ((MODE) == CEC_BitTimingErrFreeMode)) -/** - * @} - */ - -/** @defgroup CEC_BitPeriod_Mode - * @{ - */ -#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ -#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ - -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ - ((MODE) == CEC_BitPeriodFlexibleMode)) -/** - * @} - */ - - -/** @defgroup CEC_interrupts_definition - * @{ - */ -#define CEC_IT_TERR CEC_CSR_TERR -#define CEC_IT_TBTRF CEC_CSR_TBTRF -#define CEC_IT_RERR CEC_CSR_RERR -#define CEC_IT_RBTF CEC_CSR_RBTF -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ - ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) -/** - * @} - */ - - -/** @defgroup CEC_Own_Address - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) -/** - * @} - */ - -/** @defgroup CEC_Prescaler - * @{ - */ -#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) - -/** - * @} - */ - -/** @defgroup CEC_flags_definition - * @{ - */ - -/** - * @brief ESR register flags - */ -#define CEC_FLAG_BTE ((uint32_t)0x10010000) -#define CEC_FLAG_BPE ((uint32_t)0x10020000) -#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) -#define CEC_FLAG_SBE ((uint32_t)0x10080000) -#define CEC_FLAG_ACKE ((uint32_t)0x10100000) -#define CEC_FLAG_LINE ((uint32_t)0x10200000) -#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) - -/** - * @brief CSR register flags - */ -#define CEC_FLAG_TEOM ((uint32_t)0x00000002) -#define CEC_FLAG_TERR ((uint32_t)0x00000004) -#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) -#define CEC_FLAG_RSOM ((uint32_t)0x00000010) -#define CEC_FLAG_REOM ((uint32_t)0x00000020) -#define CEC_FLAG_RERR ((uint32_t)0x00000040) -#define CEC_FLAG_RBTF ((uint32_t)0x00000080) - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ - ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ - ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ - ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ - ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ - ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ - ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions - * @{ - */ -void CEC_DeInit(void); -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ITConfig(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_SetPrescaler(uint16_t CEC_Prescaler); -void CEC_SendDataByte(uint8_t Data); -uint8_t CEC_ReceiveDataByte(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessageCmd(FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint8_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h deleted file mode 100644 index 174773c..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ /dev/null @@ -1,317 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line, Medium-density and Low-density Value Line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel - only in Medium-density and Low-density Value Line devices*/ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ -#endif - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -#endif -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h deleted file mode 100644 index bb9d7f6..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h deleted file mode 100644 index 63720de..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ /dev/null @@ -1,426 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ -#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -#ifdef STM32F10X_XL -/** - * @} - */ -/** @defgroup FLASH_Boot - * @{ - */ -#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 or Bank 1, - depending on the activation of the bank */ -#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) -#endif -/** - * @} - */ -/** @defgroup FLASH_Interrupts - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ -#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ - -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#else -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ -#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ -#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ -#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)|| \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) -#else -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32F10x devices -----*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/*------------ New function used for all STM32F10x devices -----*/ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef STM32F10X_XL -/*---- New Functions used only with STM32F10x_XL density devices -----*/ -void FLASH_UnlockBank2(void); -void FLASH_LockBank2(void); -FLASH_Status FLASH_EraseAllBank2Pages(void); -FLASH_Status FLASH_GetBank2Status(void); -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h deleted file mode 100644 index 60e4b14..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_NCAK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/*======================================== - - I2C Master Events (Events grouped in order of communication) - ==========================================*/ -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/*======================================== - - I2C Slave Events (Events grouped in order of communication) - ==========================================*/ - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/*=========================== End of Events Description ==========================================*/ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occurred. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the limitations of I2C_GetFlagStatus() function (see below). - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -/** - * - ******************************************************************************* - */ - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h deleted file mode 100644 index 25b0bb5..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IWDG_H -#define __STM32F10x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions - * @{ - */ - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_IWDG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h deleted file mode 100644 index 1c025e2..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h deleted file mode 100644 index fd8beb5..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h deleted file mode 100644 index bdfa177..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_WWDG_H -#define __STM32F10x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c deleted file mode 100644 index 8155dc9..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ /dev/null @@ -1,1307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the ADC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibration registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c deleted file mode 100644 index 6501728..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_crc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c deleted file mode 100644 index 1cfc71d..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ /dev/null @@ -1,571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DAC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); - } -} -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} -#endif - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c deleted file mode 100644 index 51669ee..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ /dev/null @@ -1,866 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the FSMC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC - * NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC - * PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c deleted file mode 100644 index bc1719d..0000000 --- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ /dev/null @@ -1,799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the SDIO firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |