diff options
Diffstat (limited to 'thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker')
7 files changed, 472 insertions, 0 deletions
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf new file mode 100644 index 0000000..1efdb2b --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08003000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08003000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk new file mode 100644 index 0000000..2d9c35c --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk @@ -0,0 +1,4 @@ +-d"./settings/STM32F10x_offset.lsl" +--optimize=0 +--map-file-format=2 +$(LinkObjects) diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk new file mode 100644 index 0000000..3f877d3 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk @@ -0,0 +1,5 @@ +-d"./settings/STM32F10x_offset.lsl" +--optimize=0 +--map-file-format=2 +$(LinkObjects) +--output=.\Objects\$(Target)
\ No newline at end of file diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl new file mode 100644 index 0000000..65789ce --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl @@ -0,0 +1,174 @@ +//////////////////////////////////////////////////////////////////////////// +// +// File : stm32f103_cmsis.lsl +// +// Version : @(#)stm32f103_cmsis.lsl 1.2 09/06/04 +// +// Description : LSL file for the STMicroelectronics STM32F103, CMSIS version +// +// Copyright 2009 Altium BV +// +// NOTE: +// This file is derived from cm3.lsl and stm32f103.lsl. +// It is assumed that the user works with the ARMv7M architecture. +// Other architectures will not work with this lsl file. +// +//////////////////////////////////////////////////////////////////////////// + +// +// We do not want the vectors as defined in arm_arch.lsl +// +#define __NO_DEFAULT_AUTO_VECTORS 1 +#define __NR_OF_VECTORS 76 + + +#ifndef __STACK +# define __STACK 8k +#endif +#ifndef __HEAP +# define __HEAP 2k +#endif +#ifndef __VECTOR_TABLE_ROM_ADDR +# define __VECTOR_TABLE_ROM_ADDR 0x08003000 +#endif +#ifndef __XVWBUF +#define __XVWBUF 256 /* buffer used by CrossView */ +#endif + +#include <arm_arch.lsl> + +//////////////////////////////////////////////////////////////////////////// +// +// In the STM32F10x, 3 different boot modes can be selected +// - User Flash memory is selected as boot space +// - SystemMemory is selected as boot space +// - Embedded SRAM is selected as boot space +// +// This aliases the physical memory associated with each boot mode to Block +// 000 (0x00000000 boot memory). Even when aliased in the boot memory space, +// the related memory (Flash memory or SRAM) is still accessible at its +// original memory space. +// +// If no memory is defined yet use the following memory settings +// +#ifndef __MEMORY + +memory stm32f103flash +{ + mau = 8; + type = rom; + size = 504k; + map ( size = 504k, dest_offset=0x08003000, dest=bus:ARM:local_bus); +} + +memory stm32f103ram +{ + mau = 8; + type = ram; + size = 64k; + map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus); +} + +#endif /* __MEMORY */ + +section_layout ::linear +{ + group( contiguous ) + { + select ".bss.stack"; + select "stack"; + } +} + + +// +// Custom vector table defines interrupts according to CMSIS standard +// +# if defined(__CPU_ARMV7M__) +section_setup ::linear +{ + // vector table with handler addresses + vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR, + template = ".text.handler_address", + template_symbol = "_lc_vector_handler", + vector_prefix = "_vector_", + fill = loop, + no_inline + ) + { + vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work + vector ( id = 1, fill = "_START" ); + vector ( id = 2, optional, fill = "NMI_Handler" ); + vector ( id = 3, optional, fill = "HardFault_Handler" ); + vector ( id = 4, optional, fill = "MemManage_Handler" ); + vector ( id = 5, optional, fill = "BusFault_Handler" ); + vector ( id = 6, optional, fill = "UsageFault_Handler" ); + vector ( id = 11, optional, fill = "SVC_Handler" ); + vector ( id = 12, optional, fill = "DebugMon_Handler" ); + vector ( id = 14, optional, fill = "PendSV_Handler" ); + vector ( id = 15, optional, fill = "SysTick_Handler" ); + + // External Interrupts : + vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog + vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect + vector ( id = 18, optional, fill = "TAMPER_IRQHandler" ); // Tamper + vector ( id = 19, optional, fill = "RTC_IRQHandler" ); // RTC + vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash + vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC + vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0 + vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1 + vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2 + vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3 + vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4 + vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" ); // DMA Channel 1 + vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" ); // DMA Channel 2 + vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" ); // DMA Channel 3 + vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" ); // DMA Channel 4 + vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" ); // DMA Channel 5 + vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" ); // DMA Channel 6 + vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" ); // DMA Channel 7 + vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" ); // ADC1 and ADC2 + vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" ); // USB High Priority or CAN1 TX + vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" ); // USB LowPriority or CAN1 RX0 + vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1 + vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE + vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5 + vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" ); // TIM1 Break + vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" ); // TIM1 Update + vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" ); // TIM1 Trigger and Commutation + vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare + vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2 + vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3 + vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4 + vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event + vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error + vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event + vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error + vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1 + vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2 + vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1 + vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2 + vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3 + vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10 + vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line + vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" ); // USB Wakeup from suspend + vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" ); // TIM8 Break + vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" ); // TIM8 Update + vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" ); // TIM8 Trigger and Commutation + vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare + vector ( id = 63, optional, fill = "ADC3_IRQHandler" ); // ADC3 + vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC + vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO + vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5 + vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3 + vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4 + vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5 + vector ( id = 70, optional, fill = "TIM6_IRQHandler" ); // TIM6 + vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7 + vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" ); // DMA2 Channel1 + vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" ); // DMA2 Channel2 + vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" ); // DMA2 Channel3 + vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" ); // DMA2 Channel4 and DMA2 Channel5 + } +} +# endif diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk new file mode 100644 index 0000000..2d9c35c --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk @@ -0,0 +1,4 @@ +-d"./settings/STM32F10x_offset.lsl" +--optimize=0 +--map-file-format=2 +$(LinkObjects) diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm new file mode 100644 index 0000000..2c11b4c --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm @@ -0,0 +1,4 @@ + .section .bss.stack + .global _stacklabel +_stacklabel: + .endsec
\ No newline at end of file diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f10x_flash_offset.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f10x_flash_offset.ld new file mode 100644 index 0000000..fce0a32 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f10x_flash_offset.ld @@ -0,0 +1,250 @@ +/* +Default linker script for STM32F10x_1024K_96K +Copyright RAISONANCE S.A.S. 2008 +*/ + +/* include the common STM32F10x sub-script */ + +/* Common part of the linker scripts for STM32 devices*/ + + +/* default stack sizes. + +These are used by the startup in order to allocate stacks for the different modes. +*/ + +__Stack_Size = 1024 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + + +/* include the memory spaces definitions sub-script */ +/* +Linker subscript for STM32F10x definitions with 1024K Flash and 96K RAM */ + +/* Memory Spaces Definitions */ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K + FLASH (rx) : ORIGIN = 0x8003000, LENGTH = 1024K-0x3000 + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* higher address of the user mode stack */ +_estack = 0x20018000; + + + +/* include the sections management sub-script for FLASH mode */ +/* +Common part of the linker scripts for STR71x devices in FLASH mode +(that is, the FLASH is seen at 0) +Copyright RAISONANCE 2005 +You can use, modify and distribute thisfile freely, but without any waranty. +*/ + + + +/* Sections Definitions */ + +SECTIONS +{ + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} |