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Diffstat (limited to 'thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_sram.c')
| -rw-r--r-- | thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_sram.c | 289 |
1 files changed, 289 insertions, 0 deletions
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_sram.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_sram.c new file mode 100644 index 0000000..d463fec --- /dev/null +++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_sram.c @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file stm32l152d_eval_fsmc_sram.c + * @author MCD Application Team + * @version V1.0.1 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to drive the + * IS61WV51216BLL SRAM memory mounted on STM32L152D-EVAL board. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l152d_eval_fsmc_sram.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM32L152D_EVAL + * @{ + */ + +/** @addtogroup STM32L152D_EVAL_FSMC_SRAM + * @brief This file provides a set of functions needed to drive the + * IS61WV51216BLL SRAM memory mounted on STM32L152D-EVAL board. + * @{ + */ + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Defines + * @{ + */ +/** + * @brief FSMC Bank 1 NOR/SRAM3 + */ +#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000) +/** + * @} + */ + + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152D_EVAL_FSMC_SRAM_Private_Functions + * @{ + */ + +/** + * @brief Configures the FSMC and GPIOs to interface with the SRAM memory. + * This function must be called before any write/read operation + * on the SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOF | + RCC_AHBPeriph_GPIOG, ENABLE); + +/*-- GPIO Configuration ------------------------------------------------------*/ + /*!< SRAM Data lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | + GPIO_Pin_15; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC); + + /*!< SRAM Address lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOF, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource2, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource5, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource13, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource2, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource5, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_FSMC); + + /*!< NOE and NWE configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); + + /*!< NE3 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource10, GPIO_AF_FSMC); + + /*!< NBL0, NBL1 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; + GPIO_Init(GPIOE, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_FSMC); + +/*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 3; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /*!< Enable FSMC Bank1_SRAM Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +} + +/** + * @brief Writes a Half-word buffer to the FSMC SRAM memory. + * @param pBuffer : pointer to buffer. + * @param WriteAddr : SRAM memory internal address from which the data will be + * written. + * @param NumHalfwordToWrite : number of half-words to write. + * @retval None + */ +void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) +{ + for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */ + { + /*!< Transfer data to the memory */ + *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++; + + /*!< Increment the address*/ + WriteAddr += 2; + } +} + +/** + * @brief Reads a block of data from the FSMC SRAM memory. + * @param pBuffer : pointer to the buffer that receives the data read from the + * SRAM memory. + * @param ReadAddr : SRAM memory internal address to read from. + * @param NumHalfwordToRead : number of half-words to read. + * @retval None + */ +void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) +{ + for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */ + { + /*!< Read a half-word from the memory */ + *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr); + + /*!< Increment the address*/ + ReadAddr += 2; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |