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Diffstat (limited to 'tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c')
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c new file mode 100644 index 0000000..d982167 --- /dev/null +++ b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c @@ -0,0 +1,218 @@ +/** + ****************************************************************************** + * @file DMA/FSMC/main.c + * @author MCD Application Team + * @version V3.5.0 + * @date 08-April-2011 + * @brief Main program body. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#ifdef STM32F10X_HD_VL /* High-density Value line devices */ + #include "stm32100e_eval_fsmc_sram.h" +#else /* High- and XL-density */ + #include "stm3210e_eval_fsmc_sram.h" +#endif + +/** @addtogroup STM32F10x_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DMA_FSMC + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define BufferSize 32 +#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +DMA_InitTypeDef DMA_InitStructure; +volatile TestStatus TransferStatus; +const uint32_t SRC_Const_Buffer[BufferSize]= { + 0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10, + 0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20, + 0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30, + 0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40, + 0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50, + 0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60, + 0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70, + 0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80}; +uint8_t DST_Buffer[4*BufferSize]; +uint32_t Idx = 0; + +/* Private function prototypes -----------------------------------------------*/ +void RCC_Configuration(void); +TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f10x_xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f10x.c file + */ + + /* System Clocks Configuration */ + RCC_Configuration(); + + /* FSMC for SRAM and SRAM pins configuration */ + SRAM_Init(); + + /* Write to FSMC -----------------------------------------------------------*/ + /* DMA2 channel5 configuration */ + DMA_DeInit(DMA2_Channel5); + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer; + DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Bank1_SRAM3_ADDR; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_BufferSize = 32; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_M2M = DMA_M2M_Enable; + DMA_Init(DMA2_Channel5, &DMA_InitStructure); + + /* Enable DMA2 channel5 */ + DMA_Cmd(DMA2_Channel5, ENABLE); + + /* Check if DMA2 channel5 transfer is finished */ + while(!DMA_GetFlagStatus(DMA2_FLAG_TC5)); + + /* Clear DMA2 channel5 transfer complete flag bit */ + DMA_ClearFlag(DMA2_FLAG_TC5); + + /* Read from FSMC ----------------------------------------------------------*/ + /* Destination buffer initialization */ + for(Idx=0; Idx<128; Idx++) DST_Buffer[Idx]=0; + + /* DMA1 channel3 configuration */ + DMA_DeInit(DMA1_Channel3); + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)Bank1_SRAM3_ADDR; + DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_BufferSize = 128; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_M2M = DMA_M2M_Enable; + DMA_Init(DMA1_Channel3, &DMA_InitStructure); + + /* Enable DMA1 channel3 */ + DMA_Cmd(DMA1_Channel3, ENABLE); + + /* Check if DMA1 channel3 transfer is finished */ + while(!DMA_GetFlagStatus(DMA1_FLAG_TC3)); + + /* Clear DMA1 channel3 transfer complete flag bit */ + DMA_ClearFlag(DMA1_FLAG_TC3); + + /* Check if the transmitted and received data are equal */ + TransferStatus = Buffercmp(SRC_Const_Buffer, (uint32_t*)DST_Buffer, BufferSize); + /* TransferStatus = PASSED, if the transmitted and received data + are the same */ + /* TransferStatus = FAILED, if the transmitted and received data + are different */ + + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* Enable peripheral clocks ------------------------------------------------*/ + /* DMA1 and DMA2 clock enable */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE); + /* FSMC clock enable */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); +} + +/** + * @brief Compares two buffers. + * @param pBuffer, pBuffer1: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer identical to pBuffer1 + * FAILED: pBuffer differs from pBuffer1 + */ +TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength) +{ + while(BufferLength--) + { + if(*pBuffer != *pBuffer1) + { + return FAILED; + } + + pBuffer++; + pBuffer1++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |