wip. pcb.

4 files changed, 306 insertions, 17 deletions

diff --git a/test/doit/schematics/schematic-1.kicad_pcb b/test/doit/schematics/schematic-1.kicad_pcb
new file mode 100644
index 0000000..861eed1
--- /dev/null
+++ b/test/doit/schematics/schematic-1.kicad_pcb
@@ -0,0 +1,280 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.0-rc3+dfsg1-2)
+
+  (general
+    (thickness 1.6)
+    (drawings 0)
+    (tracks 13)
+    (zones 0)
+    (modules 3)
+    (nets 4)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.15)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 0.000001 0.000001)
+    (mod_text_width 0.15)
+    (pad_size 1.4 1.4)
+    (pad_drill 0.6)
+    (pad_to_mask_clearance 0.2)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 GND)
+  (net 2 "Net-(BT1-Pad1)")
+  (net 3 "Net-(C1-Pad1)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(BT1-Pad1)")
+    (add_net "Net-(C1-Pad1)")
+  )
+
+  (module Battery:BatteryHolder_Keystone_103_1x20mm (layer F.Cu) (tedit 5787C32C) (tstamp 5B59DAE3)
+    (at 145.975001 79.779834)
+    (descr http://www.keyelco.com/product-pdf.cfm?p=719)
+    (tags "Keystone type 103 battery holder")
+    (path /5B431438)
+    (fp_text reference BT1 (at 0 -4.3) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 9V (at 15 13) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user + (at 2.75 0) (layer F.SilkS)
+      (effects (font (size 1.5 1.5) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 15.2 0) (end 4.01 3.6) (angle -162.5) (layer F.CrtYd) (width 0.05))
+    (fp_arc (start 15.2 0) (end 4.01 -3.6) (angle 162.5) (layer F.CrtYd) (width 0.05))
+    (fp_arc (start 3.5 3.8) (end 3.5 3.25) (angle 70) (layer F.CrtYd) (width 0.05))
+    (fp_arc (start 3.5 -3.8) (end 3.5 -3.25) (angle -70) (layer F.CrtYd) (width 0.05))
+    (fp_arc (start 15.2 0) (end 4.25 3.5) (angle -162.5) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 3.5 3.8) (end 3.5 3) (angle 70) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 15.2 0) (end 4.25 -3.5) (angle 162.5) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 3.5 -3.8) (end 3.5 -3) (angle -70) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 3.5 3.8) (end 3.5 2.9) (angle 70) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 4.35 3.5) (angle -162.5) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 4.35 -3.5) (angle 162.5) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 5.2 1.3) (angle -180) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.45 -3.25) (end 3.5 -3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.45 3.25) (end 3.5 3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.45 3.25) (end -2.45 -3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.2 -3) (end 3.5 -3) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.2 3) (end -2.2 -3) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.2 3) (end 3.5 3) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 15.2 0) (end 9 1.3) (angle -170) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 13.3 1.3) (angle -150) (layer F.Fab) (width 0.1))
+    (fp_line (start 23.5712 7.7216) (end 22.6568 6.8834) (layer F.Fab) (width 0.1))
+    (fp_line (start 23.5712 -7.7216) (end 22.6314 -6.858) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 13.3 -1.3) (angle 150) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 9 -1.3) (angle 170) (layer F.Fab) (width 0.1))
+    (fp_arc (start 15.2 0) (end 5.2 -1.3) (angle 180) (layer F.Fab) (width 0.1))
+    (fp_line (start 3.5306 -2.9) (end -1.7 -2.9) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.7 2.9) (end 3.5306 2.9) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.1 -2.5) (end -2.1 2.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 0 1.3) (end 16.2 1.3) (layer F.Fab) (width 0.1))
+    (fp_line (start 16.2 -1.3) (end 0 -1.3) (layer F.Fab) (width 0.1))
+    (fp_arc (start 3.5 -3.8) (end 3.5 -2.9) (angle -70) (layer F.Fab) (width 0.1))
+    (fp_arc (start 16.2 0) (end 16.2 -1.3) (angle 180) (layer F.Fab) (width 0.1))
+    (fp_line (start 0 -1.3) (end 0 1.3) (layer F.Fab) (width 0.1))
+    (fp_arc (start -1.7 2.5) (end -2.1 2.5) (angle -90) (layer F.Fab) (width 0.1))
+    (fp_arc (start -1.7 -2.5) (end -2.1 -2.5) (angle 90) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole circle (at 20.49 0) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (pad 1 thru_hole rect (at 0 0) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)
+      (net 2 "Net-(BT1-Pad1)"))
+    (model ${KISYS3DMOD}/Battery.3dshapes/BatteryHolder_Keystone_103_1x20mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal (layer F.Cu) (tedit 5AE50EF2) (tstamp 5B59DB0A)
+    (at 201.5 64.75 270)
+    (descr "CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf")
+    (tags "CP Axial series Axial Horizontal pin pitch 25mm  length 18mm diameter 8mm Electrolytic Capacitor")
+    (path /5B4314AB)
+    (fp_text reference C1 (at 12.5 -5.12 270) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 1u (at 12.5 5.12 270) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 3.5 -4) (end 3.5 4) (layer F.Fab) (width 0.1))
+    (fp_line (start 21.5 -4) (end 21.5 4) (layer F.Fab) (width 0.1))
+    (fp_line (start 3.5 -4) (end 5.18 -4) (layer F.Fab) (width 0.1))
+    (fp_line (start 5.18 -4) (end 6.08 -3.1) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.08 -3.1) (end 6.98 -4) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.98 -4) (end 21.5 -4) (layer F.Fab) (width 0.1))
+    (fp_line (start 3.5 4) (end 5.18 4) (layer F.Fab) (width 0.1))
+    (fp_line (start 5.18 4) (end 6.08 3.1) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.08 3.1) (end 6.98 4) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.98 4) (end 21.5 4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0 0) (end 3.5 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 25 0) (end 21.5 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 5.2 0) (end 7 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.1 -0.9) (end 6.1 0.9) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.28 -2.6) (end 3.08 -2.6) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.18 -3.5) (end 2.18 -1.7) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.38 -4.12) (end 3.38 4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 21.62 -4.12) (end 21.62 4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.38 -4.12) (end 5.18 -4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 5.18 -4.12) (end 6.08 -3.22) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.08 -3.22) (end 6.98 -4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.98 -4.12) (end 21.62 -4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.38 4.12) (end 5.18 4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 5.18 4.12) (end 6.08 3.22) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.08 3.22) (end 6.98 4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.98 4.12) (end 21.62 4.12) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.44 0) (end 3.38 0) (layer F.SilkS) (width 0.12))
+    (fp_line (start 23.56 0) (end 21.62 0) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.45 -4.25) (end -1.45 4.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.45 4.25) (end 26.45 4.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 26.45 4.25) (end 26.45 -4.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 26.45 -4.25) (end -1.45 -4.25) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 12.5 0 270) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0 270) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
+      (net 3 "Net-(C1-Pad1)"))
+    (pad 2 thru_hole oval (at 25 0 270) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5B59DB1D)
+    (at 183.5 53.5 180)
+    (descr "Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
+    (tags "Resistor Axial_DIN0204 series Axial Horizontal pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm")
+    (path /5B431328)
+    (fp_text reference R1 (at 2.54 -1.92 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 10k (at 2.54 1.92 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 0.74 -0.8) (end 0.74 0.8) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.74 0.8) (end 4.34 0.8) (layer F.Fab) (width 0.1))
+    (fp_line (start 4.34 0.8) (end 4.34 -0.8) (layer F.Fab) (width 0.1))
+    (fp_line (start 4.34 -0.8) (end 0.74 -0.8) (layer F.Fab) (width 0.1))
+    (fp_line (start 0 0) (end 0.74 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 5.08 0) (end 4.34 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.62 -0.92) (end 4.46 -0.92) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.62 0.92) (end 4.46 0.92) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.95 -1.05) (end -0.95 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.95 1.05) (end 6.03 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.03 1.05) (end 6.03 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.03 -1.05) (end -0.95 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 2.54 0 180) (layer F.Fab)
+      (effects (font (size 0.72 0.72) (thickness 0.108)))
+    )
+    (pad 1 thru_hole circle (at 0 0 180) (size 1.4 1.4) (drill 0.7) (layers *.Cu *.Mask)
+      (net 3 "Net-(C1-Pad1)"))
+    (pad 2 thru_hole oval (at 5.08 0 180) (size 1.4 1.4) (drill 0.7) (layers *.Cu *.Mask)
+      (net 2 "Net-(BT1-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (segment (start 167.965 81.279833) (end 174.529833 81.279833) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 166.465001 79.779834) (end 167.965 81.279833) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 174.529833 81.279833) (end 189 95.75) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 195.5 95.75) (end 201.5 89.75) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 189 95.75) (end 195.5 95.75) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 145.975001 78.029834) (end 145.75 77.804833) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 145.975001 79.779834) (end 145.975001 78.029834) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 145.75 77.804833) (end 145.75 62.75) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 155 53.5) (end 178.42 53.5) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 145.75 62.75) (end 155 53.5) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 201.5 63.3) (end 201.5 64.75) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 191.7 53.5) (end 201.5 63.3) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 183.5 53.5) (end 191.7 53.5) (width 0.25) (layer F.Cu) (net 3))
+
+)
diff --git a/test/doit/schematics/schematic-1.pro b/test/doit/schematics/schematic-1.pro
new file mode 100644
index 0000000..dd201c7
--- /dev/null
+++ b/test/doit/schematics/schematic-1.pro
@@ -0,0 +1,7 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
diff --git a/test/doit/schematics/schematic-1.sch b/test/doit/schematics/schematic-1.sch
index a805e83..9efffc4 100644
--- a/test/doit/schematics/schematic-1.sch
+++ b/test/doit/schematics/schematic-1.sch
@@ -14,34 +14,34 @@ Comment3 ""
 Comment4 ""
 $EndDescr
 $Comp
-L Device:R R?
+L Device:R R1
 U 1 1 5B431328
 P 4400 2600
-F 0 "R?" V 4193 2600 50  0000 C CNN
+F 0 "R1" V 4193 2600 50  0000 C CNN
 F 1 "10k" V 4284 2600 50  0000 C CNN
-F 2 "" V 4330 2600 50  0001 C CNN
+F 2 "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal" V 4330 2600 50  0001 C CNN
 F 3 "~" H 4400 2600 50  0001 C CNN
 	1    4400 2600
 	0    1    1    0   
 $EndComp
 $Comp
-L Device:Battery_Cell BT?
+L Device:Battery_Cell BT1
 U 1 1 5B431438
 P 3700 2900
-F 0 "BT?" H 3818 2996 50  0000 L CNN
+F 0 "BT1" H 3818 2996 50  0000 L CNN
 F 1 "9V" H 3818 2905 50  0000 L CNN
-F 2 "" V 3700 2960 50  0001 C CNN
+F 2 "Battery:BatteryHolder_Keystone_103_1x20mm" V 3700 2960 50  0001 C CNN
 F 3 "~" V 3700 2960 50  0001 C CNN
 	1    3700 2900
 	1    0    0    -1  
 $EndComp
 $Comp
-L Device:C C?
+L Device:C C1
 U 1 1 5B4314AB
 P 5000 2850
-F 0 "C?" H 5115 2896 50  0000 L CNN
+F 0 "C1" H 5115 2896 50  0000 L CNN
 F 1 "1u" H 5115 2805 50  0000 L CNN
-F 2 "" H 5038 2700 50  0001 C CNN
+F 2 "Capacitor_THT:CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal" H 5038 2700 50  0001 C CNN
 F 3 "~" H 5000 2850 50  0001 C CNN
 	1    5000 2850
 	1    0    0    -1  
@@ -51,10 +51,10 @@ Wire Wire Line
 Wire Wire Line
 	5000 3100 5000 3000
 $Comp
-L power:GND #PWR?
+L power:GND #PWR0101
 U 1 1 5B4315FE
 P 3700 3200
-F 0 "#PWR?" H 3700 2950 50  0001 C CNN
+F 0 "#PWR0101" H 3700 2950 50  0001 C CNN
 F 1 "GND" H 3705 3027 50  0000 C CNN
 F 2 "" H 3700 3200 50  0001 C CNN
 F 3 "" H 3700 3200 50  0001 C CNN
diff --git a/test/doit/test_doit.py b/test/doit/test_doit.py
index 7708ca7..a379c97 100644
--- a/test/doit/test_doit.py
+++ b/test/doit/test_doit.py
@@ -1,37 +1,39 @@
-import logging
 import os
 import os.path
-import pytest
-import logging
 
 filedir = os.path.dirname(os.path.abspath(__file__))
 schematics_dir = os.path.join(filedir, "schematics")
 
+
 def find_task(tasks, name: str):
     t = next((t for t in tasks if t["name"] == name), None)
-    assert(t is not None)
+    assert t is not None, "Could not find task named {}".format(name)
     return t
 
+
 def exec_task(task):
     targets = task["targets"]
     for a in task["actions"]:
         if isinstance(a, str):
             cmd = a % dict(targets=" ".join(targets))
             ret = os.system(cmd)
-            assert(ret == 0)
+            assert (ret == 0)
         else:
             a()
 
+
 def test_doit(tmpdir, caplog):
     from ee.kicad.doit import KicadDoitTasks
 
     args = dict(
         sch=os.path.join(schematics_dir, "schematic-1.sch"),
+        kicad_pcb=os.path.join(schematics_dir, "schematic-1.kicad_pcb"),
         data_set_dir=os.path.join(tmpdir, "ee"),
     )
     tasks = list(KicadDoitTasks(**args).tasks())
-    assert(len(tasks) > 1)
+    assert (len(tasks) > 1)
     exec_task(find_task(tasks, "kicad-sch-to-data-set"))
+    exec_task(find_task(tasks, "kicad-pcb-to-data-set"))
     exec_task(find_task(tasks, "kicad-create-component-data-set"))
 
 # thirdparty/olinuxino/HARDWARE/A64-OLinuXino/A64-OLinuXino_Rev_C/A64-OlinuXino_Rev_C.sch