o A start of a kicad_pcb parser.

6 files changed, 708 insertions, 0 deletions

diff --git a/test/kicad_pcb/parser-1-cache.lib b/test/kicad_pcb/parser-1-cache.lib
new file mode 100644
index 0000000..80c02f5
--- /dev/null
+++ b/test/kicad_pcb/parser-1-cache.lib
@@ -0,0 +1,77 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Conn_01x02
+#
+DEF Conn_01x02 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Conn_01x02" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_??x*mm*
+ Connector*:*1x??x*mm*
+ Pin?Header?Straight?1X*
+ Pin?Header?Angled?1X*
+ Socket?Strip?Straight?1X*
+ Socket?Strip?Angled?1X*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/test/kicad_pcb/parser-1.kicad_pcb b/test/kicad_pcb/parser-1.kicad_pcb
new file mode 100644
index 0000000..b8efabc
--- /dev/null
+++ b/test/kicad_pcb/parser-1.kicad_pcb
@@ -0,0 +1,335 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.7+dfsg1-1)
+
+  (general
+    (links 5)
+    (no_connects 0)
+    (area 139.649999 101.549999 152.450001 109.270001)
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 14)
+    (zones 0)
+    (modules 4)
+    (nets 4)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.2)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.2)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x00030_80000001)
+      (usegerberextensions false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(C1-Pad1)")
+  (net 2 "Net-(J1-Pad2)")
+  (net 3 GND)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(C1-Pad1)")
+    (add_net "Net-(J1-Pad2)")
+  )
+
+  (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 59958EE7) (tstamp 5A29152D)
+    (at 149.86 106.68 180)
+    (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
+    (tags "capacitor 0603")
+    (path /5A2915AE)
+    (attr smd)
+    (fp_text reference C1 (at 0 -1.5 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value C (at 0 1.5 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.4 0.65) (end -1.4 0.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.4 0.65) (end 1.4 -0.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.4 -0.65) (end -1.4 0.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.4 -0.65) (end 1.4 -0.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_text user %R (at 0 0 180) (layer F.Fab)
+      (effects (font (size 0.3 0.3) (thickness 0.075)))
+    )
+    (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(C1-Pad1)"))
+    (model Capacitors_SMD.3dshapes/C_0603.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5A291533)
+    (at 142.24 106.68 180)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5A2914CA)
+    (fp_text reference J1 (at 0 -2.33 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02 (at 0 4.87 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 1.27 270) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(J1-Pad2)"))
+    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistors_SMD:R_0603 (layer F.Cu) (tedit 58E0A804) (tstamp 5A291539)
+    (at 146.05 104.14)
+    (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
+    (tags "resistor 0603")
+    (path /5A29147F)
+    (attr smd)
+    (fp_text reference R1 (at 0 -1.45) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value R (at 0 1.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 0.4 0.4) (thickness 0.075)))
+    )
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.68) (end -0.5 0.68) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.25 -0.7) (end 1.25 -0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 -0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.25 0.7) (end 1.25 -0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.25 0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+    (pad 1 smd rect (at -0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+      (net 2 "Net-(J1-Pad2)"))
+    (pad 2 smd rect (at 0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistors_SMD:R_0603 (layer F.Cu) (tedit 58E0A804) (tstamp 5A29153F)
+    (at 146.05 106.68 180)
+    (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
+    (tags "resistor 0603")
+    (path /5A29151D)
+    (attr smd)
+    (fp_text reference R2 (at 0 -1.45 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value R (at 0 1.5 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 180) (layer F.Fab)
+      (effects (font (size 0.4 0.4) (thickness 0.075)))
+    )
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.68) (end -0.5 0.68) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.25 -0.7) (end 1.25 -0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 -0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.25 0.7) (end 1.25 -0.7) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.25 0.7) (end -1.25 0.7) (layer F.CrtYd) (width 0.05))
+    (pad 1 smd rect (at -0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(C1-Pad1)"))
+    (pad 2 smd rect (at 0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (dimension 12.7 (width 0.3) (layer Dwgs.User)
+    (gr_text "12,700 mm" (at 146.05 97.71) (layer Dwgs.User)
+      (effects (font (size 1.5 1.5) (thickness 0.3)))
+    )
+    (feature1 (pts (xy 152.4 101.6) (xy 152.4 96.36)))
+    (feature2 (pts (xy 139.7 101.6) (xy 139.7 96.36)))
+    (crossbar (pts (xy 139.7 99.06) (xy 152.4 99.06)))
+    (arrow1a (pts (xy 152.4 99.06) (xy 151.273496 99.646421)))
+    (arrow1b (pts (xy 152.4 99.06) (xy 151.273496 98.473579)))
+    (arrow2a (pts (xy 139.7 99.06) (xy 140.826504 99.646421)))
+    (arrow2b (pts (xy 139.7 99.06) (xy 140.826504 98.473579)))
+  )
+  (gr_line (start 139.7 109.22) (end 139.7 101.6) (layer Edge.Cuts) (width 0.1))
+  (gr_line (start 152.4 109.22) (end 139.7 109.22) (layer Edge.Cuts) (width 0.1))
+  (gr_line (start 152.4 101.6) (end 152.4 109.22) (layer Edge.Cuts) (width 0.1))
+  (gr_line (start 139.7 101.6) (end 152.4 101.6) (layer Edge.Cuts) (width 0.1))
+
+  (segment (start 150.61 106.68) (end 150.585 106.68) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 150.585 106.68) (end 149.884999 105.979999) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 147.3 106.68) (end 146.8 106.68) (width 0.25) (layer F.Cu) (net 1))
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+  (segment (start 146.8 106.48) (end 146.8 104.14) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 142.24 104.14) (end 145.3 104.14) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 149.11 106.68) (end 148.085002 106.68) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 148.085002 106.68) (end 147.310001 107.455001) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 147.310001 107.455001) (end 146.289999 107.455001) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 146.289999 107.455001) (end 145.514998 106.68) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 145.514998 106.68) (end 143.34 106.68) (width 0.25) (layer F.Cu) (net 3))
+  (segment (start 143.34 106.68) (end 142.24 106.68) (width 0.25) (layer F.Cu) (net 3))
+
+  (zone (net 2) (net_name "Net-(J1-Pad2)") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
+    (connect_pads (clearance 0.508))
+    (min_thickness 0.254)
+    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
+      (pts
+        (xy 152.4 101.6) (xy 139.7 101.6) (xy 139.7 109.22) (xy 152.4 109.22)
+      )
+    )
+    (filled_polygon
+      (pts
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+        (xy 151.613162 106.069683) (xy 151.47409 105.853559) (xy 151.26189 105.708569) (xy 151.01 105.65756) (xy 150.637362 105.65756)
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+        (xy 145.425 104.267) (xy 145.425 105.06625) (xy 145.58375 105.225) (xy 145.676309 105.225) (xy 145.909698 105.128327)
+        (xy 146.04 104.998026) (xy 146.04 105.818824) (xy 146.01409 105.778559) (xy 145.80189 105.633569) (xy 145.55 105.58256)
+        (xy 145.05 105.58256) (xy 144.814683 105.626838) (xy 144.598559 105.76591) (xy 144.493274 105.92) (xy 143.73744 105.92)
+        (xy 143.73744 105.83) (xy 143.693162 105.594683) (xy 143.55409 105.378559) (xy 143.34189 105.233569) (xy 143.233893 105.211699)
+        (xy 143.511645 104.906924) (xy 143.681476 104.49689) (xy 143.643933 104.42575) (xy 144.415 104.42575) (xy 144.415 104.71631)
+        (xy 144.511673 104.949699) (xy 144.690302 105.128327) (xy 144.923691 105.225) (xy 145.01625 105.225) (xy 145.175 105.06625)
+        (xy 145.175 104.267) (xy 144.57375 104.267) (xy 144.415 104.42575) (xy 143.643933 104.42575) (xy 143.560155 104.267)
+        (xy 142.367 104.267) (xy 142.367 104.287) (xy 142.113 104.287) (xy 142.113 104.267) (xy 140.919845 104.267)
+        (xy 140.798524 104.49689) (xy 140.968355 104.906924) (xy 141.244501 105.209937) (xy 141.154683 105.226838) (xy 140.938559 105.36591)
+        (xy 140.793569 105.57811) (xy 140.74256 105.83) (xy 140.385 105.83) (xy 140.385 103.78311) (xy 140.798524 103.78311)
+        (xy 140.919845 104.013) (xy 142.113 104.013) (xy 142.113 102.819181) (xy 142.367 102.819181) (xy 142.367 104.013)
+        (xy 143.560155 104.013) (xy 143.681476 103.78311) (xy 143.590595 103.56369) (xy 144.415 103.56369) (xy 144.415 103.85425)
+        (xy 144.57375 104.013) (xy 145.175 104.013) (xy 145.175 103.21375) (xy 145.01625 103.055) (xy 144.923691 103.055)
+        (xy 144.690302 103.151673) (xy 144.511673 103.330301) (xy 144.415 103.56369) (xy 143.590595 103.56369) (xy 143.511645 103.373076)
+        (xy 143.121358 102.944817) (xy 142.596892 102.698514) (xy 142.367 102.819181) (xy 142.113 102.819181) (xy 141.883108 102.698514)
+        (xy 141.358642 102.944817) (xy 140.968355 103.373076) (xy 140.798524 103.78311) (xy 140.385 103.78311) (xy 140.385 102.285)
+        (xy 151.715 102.285)
+      )
+    )
+  )
+)
diff --git a/test/kicad_pcb/parser-1.net b/test/kicad_pcb/parser-1.net
new file mode 100644
index 0000000..be3173a
--- /dev/null
+++ b/test/kicad_pcb/parser-1.net
@@ -0,0 +1,96 @@
+(export (version D)
+  (design
+    (source /home/trygvis/dev/org.bitbucket/solpumpa/hardware/alpha-1/env/src/ee/test/kicad_pcb/parser-1.sch)
+    (date "to. 07. des. 2017 kl. 11.22 +0100")
+    (tool "Eeschema 4.0.7+dfsg1-1")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source parser-1.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref R1)
+      (value R)
+      (footprint Resistors_SMD:R_0603)
+      (libsource (lib device) (part R))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A29147F))
+    (comp (ref J1)
+      (value Conn_01x02)
+      (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm)
+      (libsource (lib conn) (part Conn_01x02))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A2914CA))
+    (comp (ref R2)
+      (value R)
+      (footprint Resistors_SMD:R_0603)
+      (libsource (lib device) (part R))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A29151D))
+    (comp (ref C1)
+      (value C)
+      (footprint Capacitors_SMD:C_0603)
+      (libsource (lib device) (part C))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5A2915AE)))
+  (libparts
+    (libpart (lib device) (part C)
+      (description "Unpolarized capacitor")
+      (footprints
+        (fp C_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) C))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib conn) (part Conn_01x02)
+      (description "Generic connector, single row, 01x02")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_??x*mm*)
+        (fp Connector*:*1x??x*mm*)
+        (fp Pin?Header?Straight?1X*)
+        (fp Pin?Header?Angled?1X*)
+        (fp Socket?Strip?Straight?1X*)
+        (fp Socket?Strip?Angled?1X*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x02))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))))
+    (libpart (lib device) (part R)
+      (description Resistor)
+      (footprints
+        (fp R_*)
+        (fp R_*))
+      (fields
+        (field (name Reference) R)
+        (field (name Value) R))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive)))))
+  (libraries
+    (library (logical device)
+      (uri /usr/share/kicad/library/device.lib))
+    (library (logical conn)
+      (uri /usr/share/kicad/library/conn.lib)))
+  (nets
+    (net (code 1) (name "Net-(J1-Pad2)")
+      (node (ref J1) (pin 2))
+      (node (ref R1) (pin 1)))
+    (net (code 2) (name "Net-(C1-Pad1)")
+      (node (ref R1) (pin 2))
+      (node (ref R2) (pin 1))
+      (node (ref C1) (pin 1)))
+    (net (code 3) (name GND)
+      (node (ref C1) (pin 2))
+      (node (ref R2) (pin 2))
+      (node (ref J1) (pin 1)))))
\ No newline at end of file
diff --git a/test/kicad_pcb/parser-1.pro b/test/kicad_pcb/parser-1.pro
new file mode 100644
index 0000000..1711712
--- /dev/null
+++ b/test/kicad_pcb/parser-1.pro
@@ -0,0 +1,63 @@
+update=to. 07. des. 2017 kl. 11.14 +0100
+version=1
+last_client=kicad
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=switches
+LibName4=relays
+LibName5=motors
+LibName6=transistors
+LibName7=conn
+LibName8=linear
+LibName9=regul
+LibName10=74xx
+LibName11=cmos4000
+LibName12=adc-dac
+LibName13=memory
+LibName14=xilinx
+LibName15=microcontrollers
+LibName16=dsp
+LibName17=microchip
+LibName18=analog_switches
+LibName19=motorola
+LibName20=texas
+LibName21=intel
+LibName22=audio
+LibName23=interface
+LibName24=digital-audio
+LibName25=philips
+LibName26=display
+LibName27=cypress
+LibName28=siliconi
+LibName29=opto
+LibName30=atmel
+LibName31=contrib
+LibName32=valves
+[general]
+version=1
diff --git a/test/kicad_pcb/parser-1.sch b/test/kicad_pcb/parser-1.sch
new file mode 100644
index 0000000..e3212ba
--- /dev/null
+++ b/test/kicad_pcb/parser-1.sch
@@ -0,0 +1,125 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:switches
+LIBS:relays
+LIBS:motors
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L R R1
+U 1 1 5A29147F
+P 5400 3150
+F 0 "R1" V 5480 3150 50  0000 C CNN
+F 1 "R" V 5400 3150 50  0000 C CNN
+F 2 "Resistors_SMD:R_0603" V 5330 3150 50  0001 C CNN
+F 3 "" H 5400 3150 50  0001 C CNN
+	1    5400 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L Conn_01x02 J1
+U 1 1 5A2914CA
+P 4800 2900
+F 0 "J1" H 4800 3000 50  0000 C CNN
+F 1 "Conn_01x02" H 4800 2700 50  0000 C CNN
+F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm" H 4800 2900 50  0001 C CNN
+F 3 "" H 4800 2900 50  0001 C CNN
+	1    4800 2900
+	-1   0    0    1   
+$EndComp
+$Comp
+L R R2
+U 1 1 5A29151D
+P 5400 3650
+F 0 "R2" V 5480 3650 50  0000 C CNN
+F 1 "R" V 5400 3650 50  0000 C CNN
+F 2 "Resistors_SMD:R_0603" V 5330 3650 50  0001 C CNN
+F 3 "" H 5400 3650 50  0001 C CNN
+	1    5400 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5400 3300 5400 3500
+Wire Wire Line
+	5400 3800 5400 4000
+Wire Wire Line
+	5100 3900 5700 3900
+Wire Wire Line
+	5100 3900 5100 2900
+Wire Wire Line
+	5100 2900 5000 2900
+Wire Wire Line
+	5000 2800 5400 2800
+Wire Wire Line
+	5400 2800 5400 3000
+Wire Wire Line
+	5400 3400 5700 3400
+Wire Wire Line
+	5700 3400 5700 3500
+Connection ~ 5400 3400
+$Comp
+L C C1
+U 1 1 5A2915AE
+P 5700 3650
+F 0 "C1" H 5725 3750 50  0000 L CNN
+F 1 "C" H 5725 3550 50  0000 L CNN
+F 2 "Capacitors_SMD:C_0603" H 5738 3500 50  0001 C CNN
+F 3 "" H 5700 3650 50  0001 C CNN
+	1    5700 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5700 3900 5700 3800
+Connection ~ 5400 3900
+$Comp
+L GND #PWR01
+U 1 1 5A291677
+P 5400 4000
+F 0 "#PWR01" H 5400 3750 50  0001 C CNN
+F 1 "GND" H 5400 3850 50  0000 C CNN
+F 2 "" H 5400 4000 50  0001 C CNN
+F 3 "" H 5400 4000 50  0001 C CNN
+	1    5400 4000
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/test/test_parse_kicad_pcb.py b/test/test_parse_kicad_pcb.py
new file mode 100644
index 0000000..25c1957
--- /dev/null
+++ b/test/test_parse_kicad_pcb.py
@@ -0,0 +1,12 @@
+import pytest
+import os.path
+from ee.kicad import parse_kicad_pcb
+
+basedir = os.path.dirname(os.path.abspath(__file__))
+
+def test_parsing():
+    path = os.path.join(basedir, "kicad_pcb/parser-1.kicad_pcb")
+    count = 0
+    for (event, token) in parse_kicad_pcb(path):
+        count = count + 1
+    assert count == 3657