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-rw-r--r--.gitignore6
-rw-r--r--src/ee/__init__.py5
-rw-r--r--src/ee/formatting/__init__.py1
-rw-r--r--src/ee/kicad/__init__.py238
-rw-r--r--test/parser/foo.pro63
-rw-r--r--test/parser/foo.sch2663
-rw-r--r--test/parser/parser-demo-1-cache.lib47
-rw-r--r--test/parser/parser-demo-1.kicad_pcb1
-rw-r--r--test/parser/parser-demo-1.pro60
-rw-r--r--test/parser/parser-demo-1.sch68
-rw-r--r--test/test_sch.py34
11 files changed, 3182 insertions, 4 deletions
diff --git a/.gitignore b/.gitignore
index 074e9f9..a394db4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,3 +14,9 @@ ee.egg-info
demo/*/*.net
demo/*/*.raw
demo/*/*.log
+
+.tox
+.ipynb*/
+
+# KiCAD
+*.bak
diff --git a/src/ee/__init__.py b/src/ee/__init__.py
index e5519f8..b1b825b 100644
--- a/src/ee/__init__.py
+++ b/src/ee/__init__.py
@@ -1,12 +1,11 @@
import numpy as np
__all__ = [
- 'EeError',
+ 'EeException',
'read_ltspice_raw'
]
-
-class EeError(Exception):
+class EeException(Exception):
pass
diff --git a/src/ee/formatting/__init__.py b/src/ee/formatting/__init__.py
index 32eaf64..33673a1 100644
--- a/src/ee/formatting/__init__.py
+++ b/src/ee/formatting/__init__.py
@@ -1,5 +1,4 @@
import math
-from ee import EeError
__all__ = [
'e6', 'e12', 'e24', 'e48', 'e96', 'e192',
diff --git a/src/ee/kicad/__init__.py b/src/ee/kicad/__init__.py
index e69de29..9f6394d 100644
--- a/src/ee/kicad/__init__.py
+++ b/src/ee/kicad/__init__.py
@@ -0,0 +1,238 @@
+import re
+from ee import EeException
+import shlex
+from typing import List
+
+class Position(object):
+ def __init__(self, x, y):
+ self._x = x
+ self._y = y
+
+ @property
+ def x(self):
+ return _x
+
+ @property
+ def y(self):
+ return _y
+
+class ComponentField(object):
+ names = ["Name", "Reference", "Value", "Footprint", "Datasheet"]
+ def __init__(self, index, name, value, position):
+ self._index = index
+ self._name = name if index >= len(ComponentField.names) else ComponentField.names[index]
+ self._value = value
+ self._position = position
+
+ @property
+ def name(self):
+ return self._name
+
+ @property
+ def value(self):
+ return self._value
+
+ @property
+ def position(self):
+ return self._position
+
+class Component(object):
+ def __init__(self, position, timestamp, library, name, unit, ref, fields):
+ self._position = position
+ self._timestamp = timestamp
+ self._library = library
+ self._name = name
+ self._unit = unit
+ self._ref = ref
+ self._fields = fields # type List[ComponentField]
+
+ @property
+ def unit(self):
+ return self._unit
+
+ @property
+ def ref(self):
+ return self._ref
+
+ @property
+ def fields(self) -> List[ComponentField]:
+ return list(self._fields)
+
+ @property
+ def named_fields(self):
+ return [f for f in self._fields if f.name]
+
+class Sheet(object):
+ def __init__(self):
+ self._components = []
+ pass
+
+ @property
+ def components(self):
+ return frozenset(self._components)
+
+ def add_component(self, component):
+ self._components.append(component)
+
+class Library(object):
+ def __init__(self, name):
+ self.name = name
+
+class Schematic(object):
+ def __init__(self):
+ self._libraries = set()
+ self._sheets = [Sheet()]
+ pass
+
+ @property
+ def first_sheet(self):
+ return self._sheets[0]
+
+ @property
+ def libraries(self):
+ return frozenset(self._libraries)
+
+ def add_library(self, library):
+ self._libraries.add(Library(library))
+
+ # Getters
+ @property
+ def components(self):
+ a = []
+ for s in self._sheets:
+ for c in s.components:
+ a.append(c)
+ return a
+
+ def get_component(self, ref, unit = 1):
+ for c in self.components:
+ if c.ref == ref and unit == unit:
+ return c
+
+ raise KeyError("No such component: {}".format(ref))
+
+def read_schematic(path):
+ schematic = Schematic()
+ sheet = None
+
+ def descr_section(lines):
+ print("descr_section: len={}".format(len(lines)))
+ pass
+
+ def comp_section(lines):
+ print("comp_section: len={}".format(len(lines)))
+ timestamp = None
+ position = None
+ library = None
+ name = None
+ unit = None
+ fields = []
+
+ extra_lines = 0
+ for line in lines:
+ if line.startswith((' ', '\t')):
+ parts = line.strip().split(" ")
+ if extra_lines == 0:
+ pass
+ else:
+ # rotation/mirroring, x1, y1, x2, y2
+ pass
+ extra_lines += 1
+ else:
+ parts = shlex.split(line)
+ if len(parts) < 3:
+ raise EeException("Bad component line: {}".format(line))
+
+ if parts[0] == "L" and len(parts) == 3:
+ name = parts[1]
+ ref = parts[2]
+ elif parts[0] == "U" and len(parts) == 4:
+ unit = int(parts[1])
+ # parts[2] == body style
+ timestamp = parts[3]
+ elif parts[0] == "P" and len(parts) == 3:
+ position = Position(int(parts[1]), int(parts[2]))
+ elif parts[0] == "F" and len(parts) >= 10:
+ oritentation = parts[3]
+ pos = Position(int(parts[4]), int(parts[5]))
+ value = parts[2]
+ size = parts[6]
+ attributes = parts[7]
+ justify = parts[8] # One of L, R, C
+ textAttrs = parts[9] # tree characters,
+ # 0: T=top justify, B=bottom justify, C=center
+ # 1: I=italics, N=normal
+ # 2: B=bold, N=normal
+ field_name = parts[10] if len(parts) > 10 else None
+ idx = int(parts[1])
+ if len(fields) != idx:
+ raise EeException("Bad index: {}, expected={}. component={}, line={}".format(idx, len(fields), ref, line))
+ fields.append(ComponentField(idx, field_name, value, pos))
+ else:
+ raise EeException("Bad component field: '{}'".format(line))
+
+ sheet.add_component(Component(position, timestamp, library, name, unit, ref, fields))
+
+ with open(path) as f:
+ header = f.readline()
+ if not "EESchema Schematic File Version" in header:
+ raise EeException("Not a KiCAD schematic file.")
+
+ sheet = schematic.first_sheet
+
+ section_name = None
+ section = []
+
+ seen_end = False
+ while not seen_end:
+ line = f.readline()
+ if not line:
+ break
+
+ line = line.rstrip()
+
+ if section_name:
+ if line.startswith("$End"):
+ print("END SECTION: {}".format(section_name))
+ if section_name == "$Comp":
+ comp_section(section)
+ elif section_name == "$Descr":
+ descr_section(section)
+ else:
+ if line == "$EndSCHEMATIC":
+ seen_end = True
+ break
+ section_name = None
+ else:
+ section.append(line)
+ else:
+ parts = line.split(" ")
+ if line.startswith("EELAYER "):
+ pass # Legacy, ignored
+ elif line.startswith("LIBS:"):
+ schematic.add_library(line[5:])
+ elif line.startswith("$"):
+ section_name = parts[0]
+ print("SECTION: {}".format(section_name))
+ section = []
+ elif line == "Entry Wire Line":
+ f.readline() # ignore the next line for now
+ elif line.startswith("Text Label "):
+ f.readline() # ignore the next line for now
+ elif line.startswith("Text Notes "):
+ f.readline() # ignore the next line for now
+ elif line.startswith("NoConn "):
+ pass
+ elif parts[0:3] == ["Wire", "Notes", "Line"]:
+ f.readline() # ignore the next line for now
+ elif parts[0:3] == ["Wire", "Wire", "Line"]:
+ f.readline() # ignore the next line for now
+ elif parts[0:3] == ["Wire", "Bus", "Line"]:
+ f.readline() # ignore the next line for now
+ elif parts[0:2] == ["Connection", "~"]:
+ pass
+ else:
+ print("line={}, len={}, wat={}".format(line, len(line), parts[0:3]))
+ raise EeException("Bad line: {}".format(line))
+
+ return schematic
diff --git a/test/parser/foo.pro b/test/parser/foo.pro
new file mode 100644
index 0000000..52c16a1
--- /dev/null
+++ b/test/parser/foo.pro
@@ -0,0 +1,63 @@
+update=ti. 29. aug. 2017 kl. 21.41 +0200
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=foo-rescue
+LibName2=power
+LibName3=device
+LibName4=transistors
+LibName5=conn
+LibName6=linear
+LibName7=regul
+LibName8=74xx
+LibName9=cmos4000
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
diff --git a/test/parser/foo.sch b/test/parser/foo.sch
new file mode 100644
index 0000000..cfedec7
--- /dev/null
+++ b/test/parser/foo.sch
@@ -0,0 +1,2663 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:sweetzpot_misc
+LIBS:mcp6421_mcp6422_mcp6424
+LIBS:mcp6041_mcp6042_mcp6043_mcp6044
+LIBS:sweetzpot_power_symbols
+LIBS:mcp4018
+LIBS:sweetzpot_nrf52832
+LIBS:max30003
+LIBS:em7180sfp
+LIBS:MMBD4148
+LIBS:ASTMKH
+LIBS:TCR2LF
+LIBS:rateboard-2_b-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title "SweetZpot Sensor"
+Date "2017-08-04"
+Rev "2_b"
+Comp "SweetZpot AS"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+ 2200 2950 2400 2950
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+L GND #PWR043
+U 1 1 598E6B65
+P 2850 3850
+F 0 "#PWR043" H 2850 3600 50 0001 C CNN
+F 1 "GND" H 2850 3700 50 0000 C CNN
+F 2 "" H 2850 3850 50 0000 C CNN
+F 3 "" H 2850 3850 50 0000 C CNN
+ 1 2850 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2850 3750 2850 3850
+$Comp
+L GND #PWR044
+U 1 1 598E6DD6
+P 3050 3850
+F 0 "#PWR044" H 3050 3600 50 0001 C CNN
+F 1 "GND" H 3050 3700 50 0000 C CNN
+F 2 "" H 3050 3850 50 0000 C CNN
+F 3 "" H 3050 3850 50 0000 C CNN
+ 1 3050 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3050 3750 3050 3850
+$Comp
+L GND #PWR045
+U 1 1 598E6F13
+P 3250 3850
+F 0 "#PWR045" H 3250 3600 50 0001 C CNN
+F 1 "GND" H 3250 3700 50 0000 C CNN
+F 2 "" H 3250 3850 50 0000 C CNN
+F 3 "" H 3250 3850 50 0000 C CNN
+ 1 3250 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3250 3750 3250 3850
+Text Label 800 3400 0 60 ~ 0
+HR_ENABLE
+Wire Wire Line
+ 9850 6750 9750 6750
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+Connection ~ 9650 6550
+$Comp
+L C C9
+U 1 1 599B9B2C
+P 3250 3600
+F 0 "C9" H 3275 3700 50 0000 L CNN
+F 1 "1u" H 3275 3500 50 0000 L CNN
+F 2 "Capacitors_SMD:C_0402" H 3288 3450 50 0001 C CNN
+F 3 "" H 3250 3600 50 0000 C CNN
+F 4 "490-10694-2-ND" H 3250 3600 60 0001 C CNN "digikey"
+F 5 "GRM155R61C105KA12D" H 3250 3600 60 0001 C CNN "part"
+ 1 3250 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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diff --git a/test/parser/parser-demo-1-cache.lib b/test/parser/parser-demo-1-cache.lib
new file mode 100644
index 0000000..c46e7b1
--- /dev/null
+++ b/test/parser/parser-demo-1-cache.lib
@@ -0,0 +1,47 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NE5534
+#
+DEF NE5534 U 0 20 Y Y 1 F N
+F0 "U" 50 250 50 H V L CNN
+F1 "NE5534" 50 150 50 H V L CNN
+F2 "" 50 50 50 H I C CNN
+F3 "" 50 150 50 H I C CNN
+ALIAS SA5534 LM101 LM201 LM301
+$FPLIST
+ DIP*W7.62mm*
+ SOIC*3.9x4.9mm*Pitch1.27mm*
+$ENDFPLIST
+DRAW
+P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f
+X ~ 1 0 -300 200 U 50 50 1 1 I
+X - 2 -300 -100 100 R 50 50 1 1 I
+X + 3 -300 100 100 R 50 50 1 1 I
+X V- 4 -100 -300 150 U 50 50 1 1 W
+X ~ 5 100 -300 250 U 50 50 1 1 I
+X ~ 6 300 0 100 L 50 50 1 1 O
+X V+ 7 -100 300 150 D 50 50 1 1 W
+X ~ 8 0 300 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/test/parser/parser-demo-1.kicad_pcb b/test/parser/parser-demo-1.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/test/parser/parser-demo-1.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/test/parser/parser-demo-1.pro b/test/parser/parser-demo-1.pro
new file mode 100644
index 0000000..355a8cb
--- /dev/null
+++ b/test/parser/parser-demo-1.pro
@@ -0,0 +1,60 @@
+update=sø. 27. aug. 2017 kl. 00.42 +0200
+version=1
+last_client=kicad
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=microcontrollers
+LibName13=dsp
+LibName14=microchip
+LibName15=analog_switches
+LibName16=motorola
+LibName17=texas
+LibName18=intel
+LibName19=audio
+LibName20=interface
+LibName21=digital-audio
+LibName22=philips
+LibName23=display
+LibName24=cypress
+LibName25=siliconi
+LibName26=opto
+LibName27=atmel
+LibName28=contrib
+LibName29=valves
+[general]
+version=1
diff --git a/test/parser/parser-demo-1.sch b/test/parser/parser-demo-1.sch
new file mode 100644
index 0000000..0dad706
--- /dev/null
+++ b/test/parser/parser-demo-1.sch
@@ -0,0 +1,68 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L LM101 U101
+U 1 1 59A1FBDB
+P 3400 2400
+F 0 "U101" H 3450 2650 50 0000 L CNN
+F 1 "LM101 \"X\"" H 3450 2550 50 0000 L CNN
+F 2 "" H 3450 2450 50 0001 C CNN
+F 3 "" H 3450 2550 50 0001 C CNN
+F 4 "1234" H 3400 2400 60 0001 C CNN "mpn"
+ 1 3400 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L R R101
+U 1 1 59A2E082
+P 4300 2200
+F 0 "R101" V 4380 2200 50 0000 C CNN
+F 1 "10k" V 4300 2200 50 0000 C CNN
+F 2 "" V 4230 2200 50 0001 C CNN
+F 3 "" H 4300 2200 50 0001 C CNN
+ 1 4300 2200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/test/test_sch.py b/test/test_sch.py
new file mode 100644
index 0000000..a3c6915
--- /dev/null
+++ b/test/test_sch.py
@@ -0,0 +1,34 @@
+import pytest
+import sys
+import os.path
+from ee.kicad import read_schematic
+
+basedir = os.path.dirname(os.path.abspath(__file__))
+
+def dump_schema(sch):
+ print("Libraries")
+ for l in sch.libraries:
+ print("name: {}".format(l.name))
+
+ print("Components")
+ for c in sch.components:
+ if c.unit != 1:
+ continue
+ print("REF: {}, fields={}".format(c.ref if c.unit == 1 else "{}/{}".format(c.ref, c.unit), len(c.fields)))
+ for f in c.fields:
+ print(" {}={}".format(f.name, f.value))
+
+def load(path):
+ p = basedir + "/parser/" + path
+ print("p={}".format(p))
+ return read_schematic(p)
+
+def test_demo_1():
+ sch = load("parser-demo-1.sch")
+ dump_schema(sch)
+ r101 = sch.get_component("R101")
+ assert r101
+
+def test_sch():
+ sch = load("foo.sch")
+ dump_schema(sch)
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-22 23:02:49 +0000