diff options
Diffstat (limited to 'thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc')
6 files changed, 904 insertions, 0 deletions
diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_coredep.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_coredep.h new file mode 100644 index 0000000..fddf052 --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_coredep.h @@ -0,0 +1,171 @@ +/** + * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_COREDEP_H__ +#define NRFX_COREDEP_H__ + +/** + * @defgroup nrfx_coredep Core-dependent functionality + * @{ + * @ingroup nrfx + * @brief Module containing functions with core-dependent implementation, like delay. + */ + +#if defined(__NRFX_DOXYGEN__) + +/** @brief Core frequency (in MHz). */ +#define NRFX_DELAY_CPU_FREQ_MHZ +/** @brief Availability of DWT unit in the given SoC. */ +#define NRFX_DELAY_DWT_PRESENT + +#elif defined(NRF51) + #define NRFX_DELAY_CPU_FREQ_MHZ 16 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52810_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#elif defined(NRF52840_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#else + #error "Unknown device." +#endif + +/** + * @brief Function for delaying execution for a number of microseconds. + * + * The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to + * maximum uint32_t capacity divided by frequency. For example: + * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds) + * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds) + * + * @param time_us Number of microseconds to wait. + */ +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if NRFX_CHECK(NRFX_DELAY_DWT_BASED) + +#if !NRFX_DELAY_DWT_PRESENT +#error "DWT unit not present in the SoC that is used." +#endif + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + + // Save the current state of the DEMCR register to be able to restore it before exiting + // this function. Enable the trace and debug blocks (DWT is one of them). + uint32_t core_debug = CoreDebug->DEMCR; + CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; + + // Save the current state of the CTRL register in DWT block. Make sure + // that cycle counter is enabled. + uint32_t dwt_ctrl = DWT->CTRL; + DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; + + // Store start value of cycle counter. + uint32_t cyccnt_initial = DWT->CYCCNT; + + // Delay required time. + while ((DWT->CYCCNT - cyccnt_initial) < time_cycles) + {} + + // Restore preserved registers. + DWT->CTRL = dwt_ctrl; + CoreDebug->DEMCR = core_debug; +} +#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED) + + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + + #if defined(NRF51) + // The loop takes 4 cycles: 1 for SUBS and 3 for BHI. + static const uint16_t delay_bytecode[] = { + 0x3804, // SUBS r0, #4 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #elif defined(NRF52810_XXAA) + // The loop takes 7 cycles: 1 for SUBS and 2 for BHI and 2 for flash wait states. + static const uint16_t delay_bytecode[] = { + 0x3807, // SUBS r0, #7 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) || defined(NRF52840_XXAA) + // The loop takes 3 cycles: 1 for SUBS and 2 for BHI. + // Make sure that code will be cached properly, so that no extra wait states appear. + __ALIGN(16) + static const uint16_t delay_bytecode[] = { + 0x3803, // SUBS r0, #3 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #endif + + typedef void (* delay_func_t)(uint32_t); + // Set LSB to 1 to execute code in Thumb mode. + const delay_func_t delay_cycles = (delay_func_t)((((uint32_t)delay_bytecode) | 1)); + uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + delay_cycles(cycles); +} + +#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY) + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRFX_COREDEP_H__ diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs.h new file mode 100644 index 0000000..60fd4a2 --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs.h @@ -0,0 +1,56 @@ +/** + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_H__ +#define NRFX_IRQS_H__ + +#if defined(NRF51) + #include <soc/nrfx_irqs_nrf51.h> +#elif defined(NRF52810_XXAA) + #include <soc/nrfx_irqs_nrf52810.h> +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #include <soc/nrfx_irqs_nrf52832.h> +#elif defined(NRF52840_XXAA) + #include <soc/nrfx_irqs_nrf52840.h> +#else + #error "Unknown device." +#endif + +#endif // NRFX_IRQS_H__ diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf51.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf51.h new file mode 100644 index 0000000..0a20453 --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf51.h @@ -0,0 +1,136 @@ +/** + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_NRF51_H__ +#define NRFX_IRQS_NRF51_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UART0_IRQn +#define nrfx_uart_0_irq_handler UART0_IRQHandler + +// SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPI0_TWI0_IRQHandler +#else +#define nrfx_spi_0_irq_handler SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPI0_TWI0_IRQHandler +#endif + +// SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPI1_TWI1_IRQHandler +#else +#define nrfx_spi_1_irq_handler SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPI1_TWI1_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// ADC_IRQn +#define nrfx_adc_irq_handler ADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// LPCOMP_IRQn +#define nrfx_lpcomp_irq_handler LPCOMP_IRQHandler + +// SWI0_IRQn +#define nrfx_swi_0_irq_handler SWI0_IRQHandler + +// SWI1_IRQn +#define nrfx_swi_1_irq_handler SWI1_IRQHandler + +// SWI2_IRQn +#define nrfx_swi_2_irq_handler SWI2_IRQHandler + +// SWI3_IRQn +#define nrfx_swi_3_irq_handler SWI3_IRQHandler + +// SWI4_IRQn +#define nrfx_swi_4_irq_handler SWI4_IRQHandler + +// SWI5_IRQn +#define nrfx_swi_5_irq_handler SWI5_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF51_H__ diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52810.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52810.h new file mode 100644 index 0000000..7934854 --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52810.h @@ -0,0 +1,141 @@ +/** + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_NRF52832_H__ +#define NRFX_IRQS_NRF52832_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_IRQn +#define nrfx_uarte_0_irq_handler UARTE0_IRQHandler + +// TWIM0_TWIS0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_IRQHandler +#else +#define nrfx_twim_0_irq_handler TWIM0_TWIS0_IRQHandler +#define nrfx_twis_0_irq_handler TWIM0_TWIS0_IRQHandler +#endif + +// SPIM1_SPIS1_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_IRQn +#define nrfx_comp_irq_handler COMP_IRQHandler + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_IRQn +#define nrfx_swi_2_irq_handler SWI2_IRQHandler + +// SWI3_IRQn +#define nrfx_swi_3_irq_handler SWI3_IRQHandler + +// SWI4_IRQn +#define nrfx_swi_4_irq_handler SWI4_IRQHandler + +// SWI5_IRQn +#define nrfx_swi_5_irq_handler SWI5_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52832_H__ diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52832.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52832.h new file mode 100644 index 0000000..b947bdc --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52832.h @@ -0,0 +1,192 @@ +/** + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_NRF52832_H__ +#define NRFX_IRQS_NRF52832_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif + +// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif + +// NFCT_IRQn + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_LPCOMP_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler +#else +#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler +#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler +#endif + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_EGU2_IRQn +#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler + +// SWI3_EGU3_IRQn +#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler + +// SWI4_EGU4_IRQn +#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler + +// SWI5_EGU5_IRQn +#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler + +// TIMER3_IRQn +#define nrfx_timer_3_irq_handler TIMER3_IRQHandler + +// TIMER4_IRQn +#define nrfx_timer_4_irq_handler TIMER4_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + +// MWU_IRQn + +// PWM1_IRQn +#define nrfx_pwm_1_irq_handler PWM1_IRQHandler + +// PWM2_IRQn +#define nrfx_pwm_2_irq_handler PWM2_IRQHandler + +// SPIM2_SPIS2_SPI2_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#else +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#endif + +// RTC2_IRQn +#define nrfx_rtc_2_irq_handler RTC2_IRQHandler + +// I2S_IRQn +#define nrfx_i2s_irq_handler I2S_IRQHandler + +// FPU_IRQn + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52832_H__ diff --git a/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52840.h b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52840.h new file mode 100644 index 0000000..ecb7e1d --- /dev/null +++ b/thirdparty/nRF5_SDK_15.0.0_a53641a/modules/nrfx/soc/nrfx_irqs_nrf52840.h @@ -0,0 +1,208 @@ +/** + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_NRF52840_H__ +#define NRFX_IRQS_NRF52840_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif + +// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif + +// NFCT_IRQn + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_LPCOMP_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler +#else +#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler +#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler +#endif + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_EGU2_IRQn +#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler + +// SWI3_EGU3_IRQn +#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler + +// SWI4_EGU4_IRQn +#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler + +// SWI5_EGU5_IRQn +#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler + +// TIMER3_IRQn +#define nrfx_timer_3_irq_handler TIMER3_IRQHandler + +// TIMER4_IRQn +#define nrfx_timer_4_irq_handler TIMER4_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + +// MWU_IRQn + +// PWM1_IRQn +#define nrfx_pwm_1_irq_handler PWM1_IRQHandler + +// PWM2_IRQn +#define nrfx_pwm_2_irq_handler PWM2_IRQHandler + +// SPIM2_SPIS2_SPI2_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#else +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#endif + +// RTC2_IRQn +#define nrfx_rtc_2_irq_handler RTC2_IRQHandler + +// I2S_IRQn +#define nrfx_i2s_irq_handler I2S_IRQHandler + +// FPU_IRQn + +// USBD_IRQn + +// UARTE1_IRQn +#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler + +// QSPI_IRQn +#define nrfx_qspi_irq_handler QSPI_IRQHandler + +// CRYPTOCELL_IRQn + +// PWM3_IRQn +#define nrfx_pwm_3_irq_handler PWM3_IRQHandler + +// SPIM3_IRQn +#define nrfx_spim_3_irq_handler SPIM3_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52840_H__ |