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| author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-15 12:32:36 +0200 |
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| committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-15 12:32:36 +0200 |
| commit | 7d4b5b7a123bf98fd89a4607a0d18946db7caf36 (patch) | |
| tree | d52e03fc5750efc6281d1520807b15eb971835ed /Artix-7/mw.j2 | |
| parent | efb5d278f0089be5ae9a5083e92684ee922b5c2e (diff) | |
| download | semantic-sandbox-7d4b5b7a123bf98fd89a4607a0d18946db7caf36.tar.gz semantic-sandbox-7d4b5b7a123bf98fd89a4607a0d18946db7caf36.tar.bz2 semantic-sandbox-7d4b5b7a123bf98fd89a4607a0d18946db7caf36.tar.xz semantic-sandbox-7d4b5b7a123bf98fd89a4607a0d18946db7caf36.zip | |
o Better categories.
Diffstat (limited to 'Artix-7/mw.j2')
| -rw-r--r-- | Artix-7/mw.j2 | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/Artix-7/mw.j2 b/Artix-7/mw.j2 index f52262f..79691a4 100644 --- a/Artix-7/mw.j2 +++ b/Artix-7/mw.j2 @@ -1,9 +1,9 @@ = Overview = +[[Part number::{{ part["Part number"] }}]] is an FPGA from [[Manufacturer::Xilinx]]. +It belongs to the [[Category:Xilinx Artix-7 family chip|Artix-7]] family. + {|class='wikitable' -!Part number -|[[Part number::{{ part["Part number"] }}]] -|- !Logic Cells |[[Xilix logic cells::{{ part["Logic Cells"] }}]] |- @@ -50,6 +50,5 @@ {% endif %} [[Category:Generated]] -[[Category:FPGA Chip]] [[Category:Artix-7 generated data set]] |