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author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:41:30 +0200 |
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committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-13 23:41:30 +0200 |
commit | efb5d278f0089be5ae9a5083e92684ee922b5c2e (patch) | |
tree | d247025a808ba0d2575531009e60369eabb2180d /Artix-7/mw/Chip:XC7A15T.mw | |
parent | d1ff3fc433869fda9d809292394eee811e09b512 (diff) | |
download | semantic-sandbox-efb5d278f0089be5ae9a5083e92684ee922b5c2e.tar.gz semantic-sandbox-efb5d278f0089be5ae9a5083e92684ee922b5c2e.tar.bz2 semantic-sandbox-efb5d278f0089be5ae9a5083e92684ee922b5c2e.tar.xz semantic-sandbox-efb5d278f0089be5ae9a5083e92684ee922b5c2e.zip |
o Generating under the Chip namespace.
Diffstat (limited to 'Artix-7/mw/Chip:XC7A15T.mw')
-rw-r--r-- | Artix-7/mw/Chip:XC7A15T.mw | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/Artix-7/mw/Chip:XC7A15T.mw b/Artix-7/mw/Chip:XC7A15T.mw new file mode 100644 index 0000000..b7900a6 --- /dev/null +++ b/Artix-7/mw/Chip:XC7A15T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A15T]] +|- +!Logic Cells +|[[Xilix logic cells::16640]] +|- +!Slices +|[[Xilix 7 series slices::2600]] +|- +!Distributed RAM +|[[Distributed RAM::200 kB]] +|- +!RAM blocks +|[[RAM blocks::25]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::900 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::5]] +|- +!Available IO +|[[Available IO::250]] +|- +!IO banks +|[[IO banks::5]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;45]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] |