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authorTrygve Laugstøl <trygvis@inamo.no>2018-08-13 22:14:54 +0200
committerTrygve Laugstøl <trygvis@inamo.no>2018-08-13 22:14:54 +0200
commite4d7baefdfbb278b61ea31ecd5306e110ed043b2 (patch)
treed74bbdb441b01396e4c1022133ee1ab6654ba48c /Artix-7/mw
parent06e395bc68e7d959a43d583f5e481e3ab4f093bf (diff)
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o Using jinja2 for templating.
o Adjusting some field names.
Diffstat (limited to 'Artix-7/mw')
-rw-r--r--Artix-7/mw/XC7A100T.mw14
-rw-r--r--Artix-7/mw/XC7A12T.mw14
-rw-r--r--Artix-7/mw/XC7A15T.mw14
-rw-r--r--Artix-7/mw/XC7A200T.mw14
-rw-r--r--Artix-7/mw/XC7A25T.mw14
-rw-r--r--Artix-7/mw/XC7A35T.mw14
-rw-r--r--Artix-7/mw/XC7A50T.mw14
-rw-r--r--Artix-7/mw/XC7A75T.mw14
8 files changed, 56 insertions, 56 deletions
diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw
index c7ff7d1..1eca9ee 100644
--- a/Artix-7/mw/XC7A100T.mw
+++ b/Artix-7/mw/XC7A100T.mw
@@ -11,7 +11,7 @@
|[[Slices::15850]]
|-
!Distributed RAM
-|[[Distributed RAM::1188]]
+|[[Distributed RAM::1188 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::240]]
@@ -20,10 +20,10 @@
|[[RAM blocks::135]]
|-
!RAM
-|[[RAM::4860]]
+|[[RAM::4860 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::6]]
+|[[Xilix clock management tiles::6]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::6]]
|-
-!Max User I/O
-|[[Max User I/O::300]]
+!Available IO
+|[[Available IO::300]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
index 5e3006c..1a13879 100644
--- a/Artix-7/mw/XC7A12T.mw
+++ b/Artix-7/mw/XC7A12T.mw
@@ -11,7 +11,7 @@
|[[Slices::2000]]
|-
!Distributed RAM
-|[[Distributed RAM::171]]
+|[[Distributed RAM::171 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::40]]
@@ -20,10 +20,10 @@
|[[RAM blocks::20]]
|-
!RAM
-|[[RAM::720]]
+|[[RAM::720 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::3]]
+|[[Xilix clock management tiles::3]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::3]]
|-
-!Max User I/O
-|[[Max User I/O::150]]
+!Available IO
+|[[Available IO::150]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw
index 368ff22..15e7175 100644
--- a/Artix-7/mw/XC7A15T.mw
+++ b/Artix-7/mw/XC7A15T.mw
@@ -11,7 +11,7 @@
|[[Slices::2600]]
|-
!Distributed RAM
-|[[Distributed RAM::200]]
+|[[Distributed RAM::200 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::45]]
@@ -20,10 +20,10 @@
|[[RAM blocks::25]]
|-
!RAM
-|[[RAM::900]]
+|[[RAM::900 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw
index d031550..1b7b819 100644
--- a/Artix-7/mw/XC7A200T.mw
+++ b/Artix-7/mw/XC7A200T.mw
@@ -11,7 +11,7 @@
|[[Slices::33650]]
|-
!Distributed RAM
-|[[Distributed RAM::2888]]
+|[[Distributed RAM::2888 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::740]]
@@ -20,10 +20,10 @@
|[[RAM blocks::365]]
|-
!RAM
-|[[RAM::13140]]
+|[[RAM::13140 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::10]]
+|[[Xilix clock management tiles::10]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::10]]
|-
-!Max User I/O
-|[[Max User I/O::500]]
+!Available IO
+|[[Available IO::500]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw
index 182651d..78ffda6 100644
--- a/Artix-7/mw/XC7A25T.mw
+++ b/Artix-7/mw/XC7A25T.mw
@@ -11,7 +11,7 @@
|[[Slices::3650]]
|-
!Distributed RAM
-|[[Distributed RAM::313]]
+|[[Distributed RAM::313 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::80]]
@@ -20,10 +20,10 @@
|[[RAM blocks::45]]
|-
!RAM
-|[[RAM::1620]]
+|[[RAM::1620 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::3]]
+|[[Xilix clock management tiles::3]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::3]]
|-
-!Max User I/O
-|[[Max User I/O::150]]
+!Available IO
+|[[Available IO::150]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw
index b5a0cde..89a3c3b 100644
--- a/Artix-7/mw/XC7A35T.mw
+++ b/Artix-7/mw/XC7A35T.mw
@@ -11,7 +11,7 @@
|[[Slices::5200]]
|-
!Distributed RAM
-|[[Distributed RAM::400]]
+|[[Distributed RAM::400 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::90]]
@@ -20,10 +20,10 @@
|[[RAM blocks::50]]
|-
!RAM
-|[[RAM::1800]]
+|[[RAM::1800 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw
index f8b5e1b..48b575f 100644
--- a/Artix-7/mw/XC7A50T.mw
+++ b/Artix-7/mw/XC7A50T.mw
@@ -11,7 +11,7 @@
|[[Slices::8150]]
|-
!Distributed RAM
-|[[Distributed RAM::600]]
+|[[Distributed RAM::600 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::120]]
@@ -20,10 +20,10 @@
|[[RAM blocks::75]]
|-
!RAM
-|[[RAM::2700]]
+|[[RAM::2700 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw
index 429684c..0a20722 100644
--- a/Artix-7/mw/XC7A75T.mw
+++ b/Artix-7/mw/XC7A75T.mw
@@ -11,7 +11,7 @@
|[[Slices::11800]]
|-
!Distributed RAM
-|[[Distributed RAM::892]]
+|[[Distributed RAM::892 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::180]]
@@ -20,10 +20,10 @@
|[[RAM blocks::105]]
|-
!RAM
-|[[RAM::3780]]
+|[[RAM::3780 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::6]]
+|[[Xilix clock management tiles::6]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::6]]
|-
-!Max User I/O
-|[[Max User I/O::300]]
+!Available IO
+|[[Available IO::300]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}