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Diffstat (limited to 'Artix-7/mw.j2')
| -rw-r--r-- | Artix-7/mw.j2 | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Artix-7/mw.j2 b/Artix-7/mw.j2 new file mode 100644 index 0000000..2ea20c0 --- /dev/null +++ b/Artix-7/mw.j2 @@ -0,0 +1,51 @@ += {{ part["Part number"] }} = + +{|class='wikitable' +!Part number +|[[Part number::{{ part["Part number"] }}]] +|- +!Logic Cells +|[[Xilix logic cells::{{ part["Logic Cells"] }}]] +|- +!Slices +|[[Slices::{{ part["Slices"] }}]] +|- +!Distributed RAM +|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::{{ part["DSP48E1 Slices"] }}]] +|- +!RAM blocks +|[[RAM blocks::{{ part["36 Kb"] }}]] +|- +!RAM +|[[RAM::{{ part["Max (Kb)"] }} kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::{{ part["CMTs"] }}]] +|- +!PCIe +|[[PCIe::{{ part["PCIe"] }}]] +|- +!GTPs +|[[GTPs::{{ part["GTPs"] }}]] +|- +!XADC Blocks +|[[XADC Blocks::{{ part["XADC Blocks"] }}]] +|- +!IO banks +|[[IO banks::{{ part["Total I/O Banks"] }}]] +|- +!Available IO +|[[Available IO::{{ part["Max User I/O"] }}]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] + |