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+= XC7A15T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A15T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::16640]]
+|-
+!Slices
+|[[Slices::2600]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::200]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::45]]
+|-
+!18 Kb
+|[[18 Kb::50]]
+|-
+!RAM blocks
+|[[RAM blocks::25]]
+|-
+!Max
+|[[Max::900]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::5]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::4]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::5]]
+|-
+!Max User I/O
+|[[Max User I/O::250]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]