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-rw-r--r--Artix-7/mw/XC7A35T.mw34
1 files changed, 16 insertions, 18 deletions
diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw
index 0be1dad..072ffae 100644
--- a/Artix-7/mw/XC7A35T.mw
+++ b/Artix-7/mw/XC7A35T.mw
@@ -1,5 +1,7 @@
= XC7A35T =
+== Overview ==
+
{|class='wikitable'
!Part number
|[[Part number::XC7A35T]]
@@ -13,38 +15,34 @@
!Distributed RAM
|[[Distributed RAM::400 kB]]
|-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::90]]
-|-
!RAM blocks
|[[RAM blocks::50]]
|-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
|[[RAM::1800 kB]]
|-
!Clock management tiles
|[[Xilix clock management tiles::5]]
|-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::4]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::5]]
-|-
!Available IO
|[[Available IO::250]]
|-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::5]]
|-
|}
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;4]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;90]]
+
[[Category:Generated]]
[[Category:FPGA Chip]]
[[Category:Artix-7 generated data set]]