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Diffstat (limited to 'Artix-7/parts.csv')
| -rw-r--r-- | Artix-7/parts.csv | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Artix-7/parts.csv b/Artix-7/parts.csv new file mode 100644 index 0000000..5b0aaf0 --- /dev/null +++ b/Artix-7/parts.csv @@ -0,0 +1,22 @@ +#,Table 4: Artix-7 FPGA Feature Summary by Device,,,,,,,,,,,, +Part number,Logic Cells,Slices(1),Max Distributed RAM (Kb),DSP48E1 Slices(2),18 Kb,36 Kb,Max (Kb),CMTs(4),PCIe(5),GTPs,XADC Blocks,Total I/O Banks(6),Max User I/O(7) +XC7A12T,12800,2000,171,40,40,20,720,3,1,2,1,3,150 +XC7A15T,16640,2600,200,45,50,25,900,5,1,4,1,5,250 +XC7A25T,23360,3650,313,80,90,45,1620,3,1,4,1,3,150 +XC7A35T,33280,5200,400,90,100,50,1800,5,1,4,1,5,250 +XC7A50T,52160,8150,600,120,150,75,2700,5,1,4,1,5,250 +XC7A75T,75520,11800,892,180,210,105,3780,6,1,8,1,6,300 +XC7A100T,101440,15850,1188,240,270,135,4860,6,1,8,1,6,300 +XC7A200T,215360,33650,2888,740,730,365,13140,10,1,16,1,10,500 +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +#,Notes:,,,,,,,,,,,, +#,1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.,,,,,,,,,,,, +#,"2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.",,,,,,,,,,,, +#,3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.,,,,,,,,,,,, +#,4. Each CMT contains one MMCM and one PLL.,,,,,,,,,,,, +#,5. Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.,,,,,,,,,,,, +#,6. Does not include configuration Bank 0.,,,,,,,,,,,, +#,7. This number does not include GTP transceivers.,,,,,,,,,,,, |