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| author | Nicolas Pitre <nico@fluxnic.net> | 2009-10-27 01:14:33 -0400 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-10-26 23:53:21 -0700 |
| commit | 068a6c7895607a6af6758ad18bace683f6b7499d (patch) | |
| tree | c707c8238dca6fb215b86a9739861173a3444010 | |
| parent | ee8e93cb836bc01581329c5685c888c4d85e6c1b (diff) | |
| download | openocd+libswd-068a6c7895607a6af6758ad18bace683f6b7499d.tar.gz openocd+libswd-068a6c7895607a6af6758ad18bace683f6b7499d.tar.bz2 openocd+libswd-068a6c7895607a6af6758ad18bace683f6b7499d.tar.xz openocd+libswd-068a6c7895607a6af6758ad18bace683f6b7499d.zip | |
ARM: allow proper single stepping of Thumb BL and BLX instructions
Whenever an unconditional branch with the H bits set to 0b10 is met, the
offset must be combined with the offset from the following opcode and not
ignored like it is now.
A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder
would be a simpler solution. That might be true when single-stepping of
Thumb2 code is implemented. But for now this appears to be the simplest
solution to fix Thumb1 support.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
| -rw-r--r-- | src/target/arm_simulator.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 646baea7..5af2c129 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -332,6 +332,18 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si return ERROR_OK; } + + /* Deal with 32-bit BL/BLX */ + if ((opcode & 0xf800) == 0xf000) { + uint32_t high = instruction.info.b_bl_bx_blx.target_address; + retval = target_read_u16(target, current_pc+2, &opcode); + if (retval != ERROR_OK) + return retval; + retval = thumb_evaluate_opcode(opcode, current_pc, &instruction); + if (retval != ERROR_OK) + return retval; + instruction.info.b_bl_bx_blx.target_address += high; + } } /* examine instruction type */ |