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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-24 13:17:04 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-11-05 23:56:37 +0100 |
| commit | 1ebdc244941c02503fc042e538991d617157184f (patch) | |
| tree | 3580832db13d5f9a32917e68e9252bc352f70566 | |
| parent | afed39c0fe20bffcf0f289e59e80ab9d6bb40a91 (diff) | |
| download | openocd+libswd-1ebdc244941c02503fc042e538991d617157184f.tar.gz openocd+libswd-1ebdc244941c02503fc042e538991d617157184f.tar.bz2 openocd+libswd-1ebdc244941c02503fc042e538991d617157184f.tar.xz openocd+libswd-1ebdc244941c02503fc042e538991d617157184f.zip | |
cortex_a8: add mrc mcr interface.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| -rw-r--r-- | src/target/cortex_a8.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 11068ba2..29fffaeb 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -70,6 +70,11 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, int cortex_a8_assert_reset(target_t *target); int cortex_a8_deassert_reset(target_t *target); +static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value); +static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value); + target_type_t cortexa8_target = { .name = "cortex_a8", @@ -106,6 +111,8 @@ target_type_t cortexa8_target = .target_create = cortex_a8_target_create, .init_target = cortex_a8_init_target, .examine = cortex_a8_examine, + .mrc = cortex_a8_mrc, + .mcr = cortex_a8_mcr, }; /* @@ -275,6 +282,28 @@ int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2, return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2); } +static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +{ + if (cpnum!=15) + { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value); +} + +static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +{ + if (cpnum!=15) + { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value); +} + + + int cortex_a8_dap_read_coreregister_u32(target_t *target, uint32_t *value, int regnum) { |