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authorØyvind Harboe <oyvind.harboe@zylin.com>2010-03-21 19:20:26 +0100
committerØyvind Harboe <oyvind.harboe@zylin.com>2010-03-21 19:21:15 +0100
commitb7811b76795aaeacfea0473bdca2c44826f20501 (patch)
treecac4f58681b3395f985a5d904f9d1faf90e86e09
parent5dcad2d34fc40659018da2cf75ceeacd3abea860 (diff)
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arm breakpoints: amended fix comment
the handling of caches, should be moved into the breakpoint specific callbacks rather than being plonked into generic memory write fn's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
-rw-r--r--src/target/arm920t.c6
-rw-r--r--src/target/arm926ejs.c7
2 files changed, 11 insertions, 2 deletions
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 4916de1d..99f7dca9 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -567,7 +567,11 @@ int arm920t_write_memory(struct target *target, uint32_t address,
/* FIX!!!! this should be cleaned up and made much more general. The
* plan is to write up and test on arm920t specifically and
- * then generalize and clean up afterwards. */
+ * then generalize and clean up afterwards.
+ *
+ * Also it should be moved to the callbacks that handle breakpoints
+ * specifically and not the generic memory write fn's. See XScale code.
+ */
if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) &&
((size==2) || (size==4)))
{
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index ff18bae8..1f753a6e 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -579,7 +579,12 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
/* FIX!!!! this should be cleaned up and made much more general. The
* plan is to write up and test on arm926ejs specifically and
- * then generalize and clean up afterwards. */
+ * then generalize and clean up afterwards.
+ *
+ *
+ * Also it should be moved to the callbacks that handle breakpoints
+ * specifically and not the generic memory write fn's. See XScale code.
+ **/
if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
{
/* special case the handling of single word writes to bypass MMU