ARM11: remove old mrc/mcr commands

Switch to new commands in config scripts

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

5 files changed, 9 insertions, 129 deletions

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 86f5748f..8223ee94 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1502,7 +1502,7 @@ proc setc15 @{regs value@} @{
 
     echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
-    arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
+    mcr 15 [expr ($regs>>12)&0x7] \
         [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
         [expr ($regs>>8)&0x7] $value
 @}
@@ -5796,15 +5796,6 @@ Without arguments, the current settings are displayed.
 @subsection ARM11 specific commands
 @cindex ARM11
 
-@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
-Write @var{value} to a coprocessor @var{pX} register
-passing parameters @var{CRn},
-@var{CRm}, opcodes @var{opc1} and @var{opc2},
-and the MCR instruction.
-(The difference beween this and the MCR2 instruction is
-one bit in the encoding, effecively a fifth parameter.)
-@end deffn
-
 @deffn Command {arm11 memwrite burst} [value]
 Displays the value of the memwrite burst-enable flag,
 which is enabled by default. Burst writes are only used
@@ -5821,15 +5812,6 @@ which is enabled by default.
 If @var{value} is defined, first assigns that.
 @end deffn
 
-@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
-Read a coprocessor @var{pX} register passing parameters @var{CRn},
-@var{CRm}, opcodes @var{opc1} and @var{opc2},
-and the MRC instruction.
-(The difference beween this and the MRC2 instruction is
-one bit in the encoding, effecively a fifth parameter.)
-Displays the result.
-@end deffn
-
 @deffn Command {arm11 step_irq_enable}  [value]
 Displays the value of the flag controlling whether
 IRQs are enabled during single stepping;
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 6cdfa64a..9d885de4 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -2087,101 +2087,6 @@ static arm11_common_t * arm11_find_target(const char * arg)
 	return 0;
 }
 
-static int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx,
-		char *cmd, char **args, int argc, bool read)
-{
-	int retval;
-
-	if (argc != (read ? 6 : 7))
-	{
-		LOG_ERROR("Invalid number of arguments.");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	arm11_common_t * arm11 = arm11_find_target(args[0]);
-
-	if (!arm11)
-	{
-		LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	if (arm11->target->state != TARGET_HALTED)
-	{
-		LOG_WARNING("target was not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	uint32_t	values[6];
-
-	for (size_t i = 0; i < (read ? 5 : 6); i++)
-	{
-		COMMAND_PARSE_NUMBER(u32, args[i + 1], values[i]);
-
-		if (values[i] > arm11_coproc_instruction_limits[i])
-		{
-			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
-				  (long)(i + 2),
-				  arm11_coproc_instruction_limits[i]);
-			return ERROR_COMMAND_SYNTAX_ERROR;
-		}
-	}
-
-	uint32_t instr = 0xEE000010	|
-		(values[0] <<  8) |
-		(values[1] << 21) |
-		(values[2] << 16) |
-		(values[3] <<  0) |
-		(values[4] <<  5);
-
-	if (read)
-		instr |= 0x00100000;
-
-	retval = arm11_run_instr_data_prepare(arm11);
-	if (retval != ERROR_OK)
-		return retval;
-
-	if (read)
-	{
-		uint32_t result;
-		retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
-		if (retval != ERROR_OK)
-			return retval;
-
-		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
-			 (int)(values[0]),
-			 (int)(values[1]),
-			 (int)(values[2]),
-			 (int)(values[3]),
-			 (int)(values[4]), result, result);
-	}
-	else
-	{
-		retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
-		if (retval != ERROR_OK)
-			return retval;
-
-		LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
-			 (int)(values[0]), (int)(values[1]),
-			 values[5],
-			 (int)(values[2]), (int)(values[3]), (int)(values[4]));
-	}
-
-	return arm11_run_instr_data_finish(arm11);
-}
-
-static int arm11_handle_mrc(struct command_context_s *cmd_ctx,
-		char *cmd, char **args, int argc)
-{
-	return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
-}
-
-static int arm11_handle_mcr(struct command_context_s *cmd_ctx,
-		char *cmd, char **args, int argc)
-{
-	return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
-}
-
 static int arm11_mrc_inner(target_t *target, int cpnum,
 		uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
 		uint32_t *value, bool read)
@@ -2300,10 +2205,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 			"DEBUG ONLY - Hardware single stepping"
 				" (default: disabled)");
 
-	register_command(cmd_ctx, top_cmd, "mcr",
-			arm11_handle_mcr, COMMAND_ANY,
-			"Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
-
 	mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
 			NULL, COMMAND_ANY, NULL);
 	register_command(cmd_ctx, mw_cmd, "burst",
@@ -2315,9 +2216,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 			"Terminate program if transfer error was found"
 				" (default: enabled)");
 
-	register_command(cmd_ctx, top_cmd, "mrc",
-			arm11_handle_mrc, COMMAND_ANY,
-			"Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
 	register_command(cmd_ctx, top_cmd, "step_irq_enable",
 			arm11_handle_bool_step_irq_enable, COMMAND_ANY,
 			"Enable interrupts while stepping"
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 17873230..9022fafc 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
 	# We assume the interpreter latency is enough.
 
 	# Allow access to all coprocessors
-	arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
+	mcr 15 0 15 1 0 0x2001
 
 	# Disable MMU, caches, write buffer
-	arm11 mcr imx35.cpu 15 0 1 0 0 0x78
+	mcr 15 0 1 0 0 0x78
 
 	# Grant manager access to all domains
-	arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
+	mcr 15 0 3 0 0 0xFFFFFFFF
 
 	# Set ARM clock to 532 MHz, AHB to 133 MHz
 	mww 0x53F80004 0x1000
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index b5e01646..54fe07f0 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -436,22 +436,22 @@ proc initC100 {} {
     #	 */
     #	mov	r0, #0
     #	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-    arm11 mcr c100.cpu 15 0 7 7 0 0x0
+    mcr 15 0 7 7 0 0x0
     #	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-    arm11 mcr c100.cpu 15 0 8 7 0 0x0
+    mcr 15 0 8 7 0 0x0
 
     #	/*
     #	 * disable MMU stuff and caches
     #	 */
     #	mrc	p15, 0, r0, c1, c0, 0
-    arm11 mrc c100.cpu 15 0 1 0 0
+    mrc 15 0 1 0 0
     #	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
     #	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
     #	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
     #	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
     #	orr	r0, r0, #0x00400000	@ set bit 22 (U)
     #	mcr	p15, 0, r0, c1, c0, 0
-    arm11 mcr c100.cpu 15 0 1 0 0 0x401002
+    mcr 15 0 1 0 0 0x401002
     # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
     # APB init
     #    	// Setting APB Bus Wait states to 1, set post write
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index 16773fa5..bfcc6525 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -10,7 +10,7 @@ proc setc15 {regs value} {
 
 	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
 
-	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+	mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
 }