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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-25 16:05:35 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-25 16:05:35 -0800 |
| commit | 83568b6b62b3508f10aa3a51fe4ae86421ec5d27 (patch) | |
| tree | 6eb6e9aef0d8f054b60793ed3e1b24dba576fe82 /NEWS | |
| parent | 49036463dbebcd4c5722f89b86dc6cec777bab0f (diff) | |
| download | openocd+libswd-83568b6b62b3508f10aa3a51fe4ae86421ec5d27.tar.gz openocd+libswd-83568b6b62b3508f10aa3a51fe4ae86421ec5d27.tar.bz2 openocd+libswd-83568b6b62b3508f10aa3a51fe4ae86421ec5d27.tar.xz openocd+libswd-83568b6b62b3508f10aa3a51fe4ae86421ec5d27.zip | |
NEWS updates
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'NEWS')
| -rw-r--r-- | NEWS | 10 |
1 files changed, 10 insertions, 0 deletions
@@ -10,10 +10,20 @@ Boundary Scan: Target Layer: ARM - renamed "armv4_5" command prefix as "arm" + - recognize TrustZone "Secure Monitor" mode + - "arm regs" command output changed + - register names use "sp" not "r13" ARM11 - Preliminary ETM and ETB hookup - accelerated "flash erase_check" - accelerated GDB memory checksum + - support "arm regs" command + - can access all core modes and registers + Cortex-A8 + - support "arm regs" command + - can access all core modes and registers + Cortex-M3 + - Exposed DWT registers like cycle counter Flash Layer: 'flash bank' and 'nand device' take <bank_name> as first argument. |