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| author | Aaron Carroll <aaronc@cse.unsw.edu.au> | 2011-02-02 18:16:26 +1100 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-02-02 08:32:10 +0100 |
| commit | aaf145c42201496007e0fc9168d9738cb0237717 (patch) | |
| tree | 5c6b5558c15583c8e214bfd3b25983bc1beac961 /contrib/loaders/checksum/armv7m_crc.s | |
| parent | efcea8306af922d867ff93073959dad774e10f0c (diff) | |
| download | openocd+libswd-aaf145c42201496007e0fc9168d9738cb0237717.tar.gz openocd+libswd-aaf145c42201496007e0fc9168d9738cb0237717.tar.bz2 openocd+libswd-aaf145c42201496007e0fc9168d9738cb0237717.tar.xz openocd+libswd-aaf145c42201496007e0fc9168d9738cb0237717.zip | |
omap4430: fix reset sequence
* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
Diffstat (limited to 'contrib/loaders/checksum/armv7m_crc.s')
0 files changed, 0 insertions, 0 deletions